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ltc2978 1 2978fc typical application features applications description octal digital power supply manager with eeprom the ltc ? 2978 is an octal, digital power-supply monitor, supervisor, sequencer, and margin controller. eight output channels can be managed per user defned confgura - tion settings. supervisory functions include fault ov/uv threshold limits for eight output channels and one input channel. programmable fault dependencies and responses allow the power supplies to be disabled with optional retry after a fault has been detected. serial bus telemetry allows eight output voltages, one input voltage, die temperature and fault status to be monitored. in addition, odd num - bered channels can be confgured to measure the voltage across a current sense resistor. power supply sequencing, precision point-of-load voltage adjustment and margining are supported with pmbus commands. a programmable watchdog timer monitors microprocessor activity for a stalled condition and resets the microprocessor if neces - sary. the 1-wire synchronization bus supports power supply sequencing across multiple ltc digital power devices. user programmable parameters can be stored in eeprom. faults and telemetry data can be logged to eeprom for diagnostic analysis. octal power supply controller with pmbus interface n computers n network servers n industrial test and measurement n high reliability systems n medical imaging n video n i 2 c/smbus serial interface n pmbus compliant command set n confguration eeprom with crc n black box fault logging to internal eeprom n differential input, 16-bit ? adc with less than 0.25% of total unadjusted error n eight voltage servos precisely adjust output voltages using eight 10-bit dacs with soft-connect n monitors eight output voltages and one input voltage and internal die temperature n 8-channel sequencer n programmable watchdog timer n eight uv/ov v out and one v in supervisor n supports multi-channel fault management n operates autonomously without additional software n ltc2978 can be powered from 3.3v or 4.5v to 15v n available in 64-pin 9mm 9mm qfn package l , lt, ltc, ltm, polyphase, linear technology and the linear logo are registered trademarks and ltpowerplay ia a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 7382303 and 7420359. typical adc total unadjusted error vs temperature temperature (c) ?50 0 error (%) 0.005 0.015 0.020 0.025 0.035 ?35 25 55 2978 ta01b 0.010 0.030 10 85 100 ?20 ?5 40 70 adc v in = 1.8v v pwr v dd33 sda scl alertb control0 wp faultb00 share_clk v in_sns v dacp0 v sensep0 v dacm0 v sensem0 v out_en0 pwrgd wdi/resetb asel0 asel1 ltc2978* pmbus interface write-protect to/from other ltc2978s 3.3v** 4.5v < v ibus < 15v gnd to p resetb input watchdog timer interrupt *some details omitted for clarity only one of eight channels shown v in v out r20 r30 r10 2978 ta01a run/ss sgnd v fb gnd load digitally managed power supply to intermediate bus converter enable v in_en **ltc2978 may be powered from either an external 3.3v supply or the intermediate bus
ltc2978 2 2978fc table of contents features ..................................................... 1 applications ................................................ 1 typical application ........................................ 1 description .................................................. 1 absolute maximum ratings .............................. 4 order information .......................................... 4 pin confguration .......................................... 4 electrical characteristics ................................. 5 pmbus timing diagram ................................... 9 typical performance characteristics .................. 10 pin functions .............................................. 14 block diagram ............................................. 16 operation ................................................... 17 operation overview ................................................ 17 eeprom ............................................................. 17 reset ...................................................................... 18 write-protect pin .................................................... 18 other operations .................................................... 18 clock sharing ..................................................... 18 pmbus serial digital interface ................................ 19 pmbus ................................................................ 19 device address ................................................... 22 processing commands ....................................... 23 pmbus command summary ............................ 24 summary table ................................................... 24 data formats ...................................................... 28 pmbus command description .......................... 29 operation, mode and eeprom commands ............ 29 page .................................................................. 29 operation ........................................................ 30 on_off_config ................................................ 31 clear_faults .................................................. 31 write_protect ............................................... 32 store_user_all and restore_user_all . 32 capability ........................................................ 32 vout_mode ...................................................... 33 output voltage related commands ........................ 33 vout_command, vout_max, vout_margin_ high, vout_margin_low, vout_ov_fault_ limit, vout_ov_warn_limit, vout_uv_ warn_limit, vout_uv_fault_limit, power_ good_on and power_good_off .................. 33 input voltage related commands ........................... 33 vin_on, vin_off, vin_ov_fault_limit, vin_ ov_warn_limit, vin_uv_warn_limit and vin_uv_fault_limit ....................................... 33 temperature related commands ............................ 34 ot_fault_limit, ot_warn_limit, ut_warn_ limit and ut_fault_limit ............................... 34 timer limits ........................................................... 34 ton_delay, ton_rise, ton_max_fault_ limit and toff_delay ...................................... 34 fault response for voltages measured by the high speed supervisor ................................................... 35 vout_ov_fault_response and vout_uv_ fault_response ............................................. 35 fault response for values measured by the adc ... 36 ot_fault_response, ut_fault_response, vin_ov_fault_response and vin_uv_fault_ response ......................................................... 36 timed fault response ............................................ 36 ton_max_fault_response .......................... 36 status commands .................................................. 37 status_byte: ................................................... 37 status_word: ................................................. 38 status_vout ................................................... 38 status_input .................................................. 39 status_temperature .................................... 39 status_cml ..................................................... 40 status_mfr_specific .................................... 40 adc monitoring commands ................................... 41 read_vin .......................................................... 41 read_vout ....................................................... 41 read_temperature_1 .................................. 41 pmbus_revision ............................................. 41 manufacturer specifc commands .......................... 42 mfr_config_ltc2978 ..................................... 42 mfr_config_all_ltc2978 ............................ 43 mfr_faultz0_propagate, mfr_faultz1_ propagate ....................................................... 44 mfr_pwrgd_en .............................................. 45 mfr_faultb00_response, mfr_faultb01_ response, mfr_faultb10_response and mfr_faultb11_response .............................. 46 mfr_vinen_ov_fault_response ................. 47 mfr_vinen_uv_fault_response ................. 48
ltc2978 3 2978fc table of contents mfr_retry_delay .......................................... 48 mfr_restart_delay ...................................... 49 mfr_vout_peak .............................................. 49 mfr_vin_peak ................................................. 49 mfr_temperature_peak .............................. 49 mfr_dac ........................................................... 50 mfr_powergood_assertion_delay ......... 50 watchdog operation ............................................... 50 mfr_watchdog_t_first and mfr_ watchdog_t .................................................... 50 mfr_page_ff_mask ....................................... 51 mfr_pads ......................................................... 52 mfr_i2c_base_address ............................... 52 mfr_special_id .............................................. 52 mfr_special_lot ........................................... 53 mfr_vout_discharge_threshold ............. 53 mfr_common .................................................. 53 mfr_spare0 ..................................................... 53 mfr_spare2 ..................................................... 53 mfr_vout_min ................................................ 54 mfr_vin_min ................................................... 54 mfr_temperature_min ................................ 54 fault log operation ................................................ 54 mfr_fault_log_store ................................. 55 mfr_fault_log_restore ............................. 55 mfr_fault_log_clear .................................. 55 mfr_fault_log_status ................................ 55 mfr_fault_log ............................................... 56 applications information ................................ 62 overview ................................................................. 62 powering the ltc2978 ............................................ 62 setting command register values ......................... 62 sequence, servo, margin and restart operations .. 62 command units on or off .................................. 62 on sequencing ................................................... 63 on state operation ............................................. 63 servo modes ...................................................... 63 dac modes ......................................................... 63 margining ........................................................... 64 off sequencing ................................................... 64 v out off threshold voltage ................................ 64 automatic restart via mfr_restart_delay command and controln pin ........................... 64 fault management .................................................. 64 output overvoltage and undervoltage faults ..... 64 output overvoltage and undervoltage warnings 65 confguring the v in_en output ............................ 65 multichannel fault management ........................ 67 interconnect between multiple ltc2978s ............... 67 application circuits ................................................. 69 trimming and margining dc/dc converters with external feedback resistors ............................... 69 four-step resistor selection procedure for dc/dc converters with external feedback resistors ..... 69 trimming and margining dc/dc converters with a trim pin ............................................................ 70 two-step resistor and dac full-scale voltage selection procedure for dc/dc converters with a trim pin ............................................................ 70 measuring current .............................................. 71 measuring current with a sense resistor ........... 71 measuring current with inductor dcr ................ 71 single phase design example ............................ 72 measuring multiphase currents .......................... 72 multiphase design example ............................... 72 anti-aliasing filter considerations ...................... 73 sensing negative voltages ................................. 73 connecting the usb to i 2 c/smbus/pmbus controller to the ltc2978 in system ....................................... 74 ltpowerplay: an interactive gui for digital power . 76 pcb assembly and layout suggestions ................. 77 bypass capacitor placement .............................. 77 exposed pad stencil design ............................... 77 pc board layout ................................................. 77 unused adc sense inputs .................................. 77 package description ..................................... 78 revision history .......................................... 79 typical application ....................................... 80 related parts .............................................. 80
ltc2978 4 2978fc pin configuration absolute maximum ratings supply voltages: v pwr to gnd ......................................... C0.3v to 15v v in_sns to gnd ...................................... C0.3v to 15v v dd33 to gnd ....................................... C0.3v to 3.6v v dd25 to gnd ..................................... C0.3v to 2.75v digital input/output voltages: alertb, sda, scl, control0, control1 ............................................ C0.3v to 5.5v pwrgd, share_clk, wdi/resetb, wp .................... C0.3v to v dd33 + 0.3v faultb00, faultb01, faultb10, faultb11 ................................ C0.3v to v dd33 + 0.3v asel0, asel1 .......................... C0.3v to v dd33 + 0.3v analog voltages: refp ................................................... C0.3v to 1.35v refm to gnd ........................................ C0.3v to 0.3v v sensep[7:0] to gnd ................................. C0.3v to 6v v sensem[7:0] to gnd ................................ C0.3v to 6v v out_en[3:0] , v in_en to gnd .................. C0.3v to 15v v out_en[7:4] to gnd ................................. C0.3v to 6v v dacp[7:0] to gnd .................................... C0.3v to 6v v dacm[7:0] to gnd ................................ C0.3v to 0.3v operating junction temperature range: ltc2978c ................................................ 0c to 70c ltc2978i ............................................. C40c to 85c storage temperature range .................. C65c to 125c (notes 1, 2) top view 65 up package 64-lead (9mm 9mm) plastic qfn v sensem6 1 v sensep7 2 v sensem7 3 v out_en0 4 v out_en1 5 v out_en2 6 v out_en3 7 v out_en4 8 v out_en5 9 v out_en6 10 v out_en7 11 v in_en 12 dnc 13 v in_sns 14 v pwr 15 v dd33 16 48 v sensep3 47 v sensem2 46 v sensep2 45 v dacm2 44 v dacp2 43 v sensem1 42 v sensep1 41 v dacm1 40 v dacp1 39 v dacp0 38 v dacm0 37 v sensem0 36 v sensep0 35 refm 34 refp 33 asel1 64 v sensep6 63 v sensem5 62 v sensep5 61 v dacm7 60 v dacp7 59 v dacp6 58 v dacm6 57 v dacm5 56 v dacp5 55 v dacp4 54 v dacm4 53 v sensem4 52 v sensep4 51 v dacm3 50 v dacp3 49 v sensem3 v dd33 17 v dd25 18 wp 19 pwrgd 20 share_clk 21 wdi/resetb 22 faultb00 23 faultb01 24 faultb10 25 faultb11 26 sda 27 scl 28 alertb 29 control0 30 control1 31 asel0 32 t jmax = 125c, jc-top = 7c/w, jc-bottom = 1c/w exposed pad (pin 65) is gnd, must be soldered to pcb order information lead free finish tape and reel part marking* package description temperature range junction ltc2978cup#pbf ltc2978cup#trpbf ltc2978up 64-lead (9mm 9mm) plastic qfn 0c to 70c ltc2978iup#pbf ltc2978iup#trpbf ltc2978up 64-lead (9mm 9mm) plastic qfn C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. consult ltc marketing for information on non-standard lead based fnish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/
ltc2978 5 2978fc electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t j = 25c. v pwr = v in_sns = 12v, v dd33 , v dd25 and ref pins foating, unless otherwise indicated. c vdd33 = 100nf, c vdd25 = 100nf and c ref = 100nf. symbol parameter conditions min typ max units power-supply characteristics v pwr v pwr supply input operating range l 4.5 15 v i pwr v pwr supply current 4.5v v pwr 15v, v dd33 floating l 10 13 ma i vdd33 v dd33 supply current 3.13v v dd33 3.47v, v pwr = v dd33 l 10 13 ma v uvlo_vdd33 v dd33 undervoltage lockout v dd33 ramping up, v pwr = v dd33 l 2.35 2.55 2.8 v v dd33 undervoltage lockout hysteresis 120 mv v dd33 supply input operating range v pwr = v dd33 l 3.13 3.47 v regulator output voltage 4.5v v pwr 15v l 3.13 3.26 3.47 v regulator output short-circuit current v pwr = 4.5v, v dd33 = 0v l 75 90 140 ma v dd25 regulator output voltage 3.13v v dd33 3.47v l 2.35 2.5 2.6 v regulator output short-circuit current v pwr = v dd33 = 3.47v, v dd25 = 0v l 30 55 80 ma voltage reference characteristics v ref output voltage 1.232 v temperature coeffcient 3 ppm/c hysteresis (note 3) 100 ppm adc characteristics v in_adc voltage sense input range differential voltage: v in_adc = (v sensepn C v sensemn ) l 0 6 v single-ended voltage: v sensemn l C0.1 0.1 v current sense input range (odd numbered channels only) single-ended voltage: v sensepn , v sensemn l C0.1 6 v differential voltage: v in_adc l C170 170 mv n_adc voltage sense resolution uses l16 format 0v v in_adc 6v 122 v/lsb current sense resolution (odd numbered channels only) 0mv |v in_adc | < 16mv (note13) 16mv |v in_adc | < 32mv 32mv |v in_adc | < 63.9mv 63.9mv |v in_adc | < 127.9mv 127.9mv |v in_adc | 15.625 31.25 62.5 125 250 v/lsb v/lsb v/lsb v/lsb v/lsb tue_adc total unadjusted error v in_adc 1.8v (note 4 ) l 0.25 % inl_adc integral nonlinearity voltage sense mode (note 5) l 854 v current sense mode, odd numbered channels only, 15.6v/lsb (note 5) l 31.3 v dnl_adc differential nonlinearity voltage sense mode l 400 v current sense mode, odd numbered channels only l 31.3 v v os_adc offset error voltage sense mode l 250 v current sense mode, odd numbered channels only l 35 v gain_adc gain error voltage sense mode, v in_adc = 6v l 0.2 % current sense mode, odd numbered channels only, v in_adc = 0.17v l 0.2 %
ltc2978 6 2978fc electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t j = 25c. v pwr = v in_sns = 12v; v dd33 , v dd25 and ref pins foating, unless otherwise indicated. c vdd33 = 100nf, c vdd25 = 100nf and c ref = 100nf. symbol parameter conditions min typ max units t conv_adc conversion time voltage sense mode (note 6) 6.15 ms current sense mode (note 6) 24.6 ms temperature input (note 6) 24.6 ms c in_adc input sampling capacitance 1 pf f in_adc input sampling frequency 62.5 khz i in_adc input leakage current v in_adc = 0v, 0v v commonmode 6v, current sense mode l 0.5 a differential input current v in_adc = 0.17v, current sense mode l 80 250 na v in_adc = 6v, voltage sense mode l 10 15 a voltage buffered idac output characteristics n_v dacp resolution 10 bits v fs_vdacp full-scale output voltage (programmable) dac code = 0x3ff dac polarity = 1 buffer gain setting_0 buffer gain setting_1 l l 1.32 2.53 1.38 2.65 1.44 2.77 v v inl_v dacp integral nonlinearity (note 7) l 2 lsb dnl_v dacp differential nonlinearity (note 7) l 2.4 lsb v os_vdacp offset voltage (note 7) l 10 mv v dacp load regulation (v dacpn C v dacmn ) v dacpn = 2.65v, i vdacpn sourcing = 2ma 100 ppm/ma v dacpn = 0.1v, i vdacpn sinking = 2ma 100 ppm/ma psrr (v dacpn C v dacmn ) dc: 3.13v v dd33 3.47v, v pwr = v dd33 60 db 100mv step in 20ns with 50pf load 40 db dc cmrr (v dacpn C v dacmn ) C0.1v v dacmn 0.1v 60 db leakage current v dacpn hi-z, 0v v dacpn 6v l 100 na short-circuit current low v dacpn shorted to gnd l C10 C4 ma short-circuit current high v dacpn shorted to v dd33 l 4 10 ma c out output capacitance v dacpn hi-z 10 pf t s_vdacp dac output update rate fast servo mode 250 s voltage supervisor characteristics v in_vs input voltage range (programmable) v in_vs = (v sensepn C v sensemn ) low resolution mode high resolution mode l l 0 0 6 3.8 v v single-ended voltage: v sensemn l C0.1 0.1 v n_vs voltage sensing resolution 0v to 3.8v range: high resolution mode 4 mv/lsb 0v to 6v range: low resolution mode 8 mv/lsb tue_vs total unadjusted error 2v v in_vs 6v, low resolution mode l 1.25 % 1.5v < v in_vs 3.8v, high resolution mode l 1.0 % 0.8v v in_vs 1.5v, high resolution mode l 1.5 % t s_vs update rate 12.21 s v in_sns input characteristics v vin_sns v in_sns input voltage range l 0 15 v r vin_sns v in_sns input resistance l 70 90 110 k
ltc2978 7 2978fc electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t j = 25c. v pwr = v in_sns = 12v; v dd33 , v dd25 and ref pins foating, unless otherwise indicated. c vdd33 = 100nf, c vdd25 = 100nf and c ref = 100nf. symbol parameter conditions min typ max units tue vin_sns v in_on , v in_off threshold total unadjusted error 3v v vin_sns 8v l 2.0 % v vin_sns > 8v l 1.0 % read_v in total unadjusted error 3v v vin_sns 8v l 1.5 % v vin_sns > 8v l 1.0 % voltage buffered idac soft-connect comparator characteristics v os_cmp offset voltage l 3 18 mv temperature sensor characteristics tue_ts total unadjusted error 1 c v out enable output (v out_en [3:0]) characteristics v vout_enn output high voltage (note 12) i vout_enn = C5a, v dd33 = 3.3v l 11.6 12.5 14.7 v i vout_enn output sourcing current v vout_enn pull-up enabled, v vout_enn = 1v l C5 C6 C8 a output sinking current strong pull-down enabled, v vout_enn = 0.4v l 3 5 8 ma weak pull-down enabled, v vout_enn = 0.4v l 33 50 60 a output leakage current internal pull-up disabled, 0v v vout_enn 15v l 1 a v out enable output (v out_en [7:4]) characteristics i vout_enn output sinking current strong pull-down enabled, v out_enn = 0.1v l 3 6 9 ma output leakage current 0v v vout_enn 6v l 1 a v in enable output (v in_en ) characteristics v vin_en output high voltage i vin_en = C5a, v dd33 = 3.3v l 11.6 12.5 14.7 v i vin_en output sourcing current v in_en pull-up enabled, v vin_en = 1v l C5 C6 C8 a output sinking current v vin_en = 0.4v l 3 5 8 ma leakage current internal pull-up disabled, 0v v vin_en 15v l 1 a eeprom characteristics endurance (notes 8, 11) 0c < t j < 85c during eeprom write operations l 10,000 cycles retention (notes 8, 11) t j < 85c l 10 years mass_write mass write operation time (note 9) store_user_all, 0c < t j < 85c during eeprom write operations l 440 4100 ms digital inputs scl, sda, control0, control1, wdi/resetb, faultb00, faultb01, faultb10, faultb11, wp v ih high level input voltage l 2.1 v v il low level input voltage l 1.5 v v hyst input hysteresis 20 mv i leak input leakage current 0v v pin 5.5v, sda, scl, controlx pins only l 2 a 0v v pin v dd33 + 0.3v, faultbxx, wdi/resetb, wp pins only l 2 a t sp pulse width of spike suppressed faultbxx, controlx pins only 10 s sda, scl pins only 98 ns t fault_min minimum low pulse width for externally generated faults 110 ms
ltc2978 8 2978fc electrical characteristics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t j = 25c. v pwr = v in_sns = 12v; v dd33 , v dd25 and ref pins foating, unless otherwise indicated. c vdd33 = 100nf, c vdd25 = 100nf and c ref = 100nf. symbol parameter conditions min typ max units t resetb pulse width to assert reset v wdi/resetb 1.5v l 300 s t wdi pulse width to reset watchdog timer v wdi/resetb 1.5v l 0.3 200 s f wdi watchdog interrupt input frequency l 1 mhz c in digital input capacitance 10 pf digital input share_clk v ih high level input voltage l 1.6 v v il low level input voltage l 0.8 v f share_clk_in input frequency operating range l 90 110 khz t low assertion low time v share_clk < 0.8v l 0.825 1.1 s t rise rise time v share_clk < 0.8v to v share_clk > 1.6v l 450 ns i leak input leakage current 0v v share_clk v dd33 + 0.3v l 1 a c in input capacitance 10 pf digital outputs sda, alertb, pwrgd, share_clk, faultb00, faultb01, faultb10, faultb11 v ol digital output low voltage i sink = 3ma l 0.4 v f share_clk_out output frequency operating range 5.49k pull-up to v dd33 l 90 100 110 khz digital inputs asel0,asel1 v ih input high threshold voltage l v dd33 C 0.5 v v il input low threshold voltage l 0.5 v i ih,il high, low input current asel[1:0] = 0, v dd33 l 95 a i ih, z hi-z input current l 24 a c in input capacitance 10 pf serial bus timing characteristics f scl serial clock frequency (note 10) l 10 400 khz t low serial clock low period (note 10) l 1.3 s t high serial clock high period (note 10) l 0.6 s t buf bus free time between stop and start (note 10) l 1.3 s t hd,sta start condition hold time (note 10) l 600 ns t su,sta start condition setup time (note 10) l 600 ns t su,sto stop condition setup time (note 10) l 600 ns t hd,dat data hold time (ltc2978 receiving data) (note 10) l 0 ns data hold time (ltc2978 transmitting data) (note 10) l 300 900 ns t su,dat data setup time (note 10) l 100 ns t sp pulse width of spike suppressed (note 10) 98 ns t timeout_bus time allowed to complete any pmbus command after which time sda will be released and command terminated longer timeout = 0 longer timeout = 1 l l 25 200 35 280 ms ms
ltc2978 9 2978fc note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating for extended periods may affect device reliability and lifetime. note 2: all currents into device pins are positive. all currents out of device pins are negative. all voltages are referenced to ground unless otherwise specifed. if power is supplied to the chip via the v dd33 pin only, connect v pwr and v dd33 pins together. note 3: hysteresis in the output voltage is created by package stress that differs depending on whether the ic was previously at a higher or lower temperature. output voltage is always measured at 25c, but the ic is cycled to 85c or C40c before successive measurements. hysteresis is roughly proportional to the square of the temperature change. note 4: tue(%) is defned as: gain error (%) + 100 ? (inl + v os )/v in . note 5: integral nonlinearity (inl) is defned as the deviation of a code from a straight line passing through the actual endpoints of the transfer curve (0v and 6v). the deviation is measured from the center of the quantization band. note 6: the time between successive adc conversions (latency of the adc) for any given channel is given as: 36.9ms + (6.15ms ? number of adc channels confgured in low resolution mode) + (24.6ms ? number of adc channels confgured in high resolution mode). electrical characteristics note 7: nonlinearity is defned from the frst code that is greater than or equal to the maximum offset specifcation to full-scale code, 1023. note 8: eeprom endurance and retention are guaranteed by design, characterization and correlation with statistical process controls. the minimum retention specifcation applies for devices whose eeprom has been cycled less than the minimum endurance specifcation. note 9: the ltc2978 will not acknowledge any pmbus commands while a mass write operation is being executed. this includes the store_user_all and mfr_fault_log_store commands or a fault log store initiated by a channel faulting off. note 10: maximum capacitive load, c b , for scl and sda is 400pf. data and clock rise time (t r ) and fall time (t f ) are: (20 + 0.1 ? c b ) (ns) < t r < 300ns and (20 + 0.1 ? c b ) (ns) < t f < 300ns. c b = capacitance of one bus line in pf. scl and sda external pull-up voltage, v io , is 3.13v < v io < 5.5v. note 11: eeprom endurance and retention will be degraded when t j > 85c. note 12: output enable pins are charge pumped from v dd33 . note 13: the current sense resolution is determined by the l11 format and the mv units of the returned value. for example a full scale value of 170mv returns a l11 value of 0xf2a8 = 680 ? 2 C2 = 170. this is the lowest range that can represent this value without overfowing the l11 mantissa and the resolution for 1lsb in this range is 2 C2 mv = 250v. each successively lower range improves resolution by cutting the lsb size in half. pmbus timing diagram sda scl t hd(sta) t hd(dat) t su(sta) t su(sto) t su(dat) t low t hd(sda) t sp t buf start condition stop condition repeated start condition start condition t r t f t r t f t high 2978 td
ltc2978 10 2978fc typical performance characteristics reference voltage vs temperature temperature sensor error vs temperature adc total unadjusted error vs temperature adc zero code center offset voltage vs temperature adc-inl adc-dnl temperature (c) ?50 reference output voltage (v) 40 55 70 85 1.2355 1.2350 1.2345 1.2340 1.2335 1.2330 1.2325 1.2320 1.2315 1.2310 2978 g01 ?35 ?20 ?5 10 25 100 three typical parts temperature (c) ?50 error (c) 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 70 2978 g02 ?20 10 40 100 55 ?35 ?5 25 85 temperature (c) ?50 0 error (%) 0.005 0.015 0.020 0.025 0.035 ?35 25 55 2978 g03 0.010 0.030 10 85 100 ?20 ?5 40 70 adc v in = 1.8v temperature (c) ?50 v os (v) 40 55 70 85 0 ?20 ?40 ?60 ?80 ?100 ?120 ?140 ?160 ?180 2978 g04 ?35 ?20 ?5 10 25 100 voltage sense mode input voltage (v) ?0.2 error (lsbs) 5.8 3.0 2.5 2.0 1.5 1.0 0.5 0 ?0.5 ?1.0 ?1.5 2978 g05 0.8 1.8 2.8 3.8 4.8 122v/lsb input voltage (v) ?0.2 error (lsbs) 5.8 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 2978 g06 0.8 1.8 2.8 3.8 4.8 122v/lsb adc rejection vs frequency at v in adc rejection vs frequency at v in (zoom) adc rejection vs frequency at v in (current sense mode) frequency (hz) ?120 rejection (db) ?80 ?40 0 ?100 ?60 ?20 12500 25000 37500 50000 2978 g07 62500 0 frequency (hz) 0 ?120 rejection (db) ?100 ?80 ?60 ?40 ?20 0 3125 6250 9375 12500 2978 g08 frequency (hz) ?120 rejection (db) ?80 ?40 0 ?100 ?60 ?20 12500 25000 37500 50000 2978 g09 62500 0
ltc2978 11 2978fc adc noise histogram voltage supervisor total unadjusted error vs temperature input sampling current vs differential input voltage dac full-scale output voltage vs temperature adc rejection vs frequency at v in (current sense mode, zoom) read_v out (v) ?20 0 number of readings 200 400 600 800 1000 1200 ?10 0 10 20 2978 g11 v in = 0v high resolution mode temperature (c) ?50 error (%) 0 ?0.05 ?0.10 ?0.15 ?0.20 ?0.25 ?0.30 ?0.35 ?0.40 70 2978 g12 ?20 10 40 100 55 ?35 ?5 25 85 v in = 0.8v high resolution mode input voltage (v) 0 0 input sampling current (a) 1 3 4 5 4 9 2978 g13 2 2 1 5 3 6 6 7 8 temperature (c) ?50 output voltage (v) 2.698 2.696 2.694 2.692 2.690 2.688 2.686 2.684 2.682 2.680 2.678 70 2978 g15 ?20?35 10?5 40 55 85 25 100 frequency (hz) 0 ?120 rejection (db) ?100 ?80 ?60 ?40 ?20 0 3125 6250 9375 12500 2978 g10 adc high resolution mode differential input current differential input voltage (mv) 0 0 differential input current (na) 10 30 40 50 120 140 160 90 2978 g14 20 60 20 80 40 100 180 60 70 80 typical performance characteristics dac offset voltage vs temperature dac-inl dac dnl temperature (c) ?50 offset error (mv) 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 70 2978 g16 ?20?35 10?5 40 55 85 25 100 dac code 0 error (lsbs) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 800 2978 g17 200 400 600 1000 dac code 0 error (lsbs) 1.0 0.8 0.6 0.4 0.2 0 ?0.2 ?0.4 ?0.6 ?0.8 ?1.0 800 2978 g18 200 400 600 1000
ltc2978 12 2978fc typical performance characteristics dac load regulation (sourcing) dac load regulation (sinking) dac short-circuit current vs temperature dac transient response to 1lsb dac code change dac soft connect transient response when transitioning from hi-z state to on state dac soft connect transient response when transitioning from on state to hi-z state current (ma) 0 2.678 output voltage (v) 2.680 2.684 2.686 2.688 2.698 85c 2.692 ?0.5 ?1 ?1.25 2978 g19 2.682 2.694 2.696 2.690 ?0.25 ?0.75 ?1.50 1.75 ?2 25c ?40c current (ma) 0 output voltage (v) 0.5 1 1.25 2 2978 g20 0.25 0.75 1.5 1.75 0.1038 0.1036 0.1034 0.1032 85c 25c 0.1030 0.1028 0.1026 ?40c temperature (c) 8.70 short-circuit current (ma) 8.80 8.90 9.00 8.75 8.85 8.95 ?20 10 40 70 2978 g21 100 ?35?50 ?5 25 55 85 10mv/div 500s/div 100k series resistance on code: ?h1ff 2978 g23 hi-z connected 10mv/div 500s/div 100k series resistance on code: ?h1ff 2978 g24 connected hi-z 500v/div 2s/div 2978 g22 code ?h1ff code ?h200 v dd33 regulator short-circuit current vs temperature v dd33 regulator line regulation v pwr (v) 4.5 ?500 ?v dd33 (ppm) ?400 ?200 ?100 0 10.5 400 85c 25c ?40c 2978 g26 ?300 7.5 6 12 13.5 9 15 100 200 300 temperature (c) ?50 short-circuit current (ma) ?86 ?88 ?90 ?92 ?94 ?96 ?98 ?100 ?102 70 2978 g27 ?20 10 40 100 55 ?35 ?5 25 85 v dd33 regulator output voltage vs temperature temperature (c) ?50 v dd33 output voltage (v) 3.275 3.270 3.265 3.260 3.255 3.250 3.245 3.240 3.235 70 2978 g25 ?20 10 40 100 55 ?35 ?5 25 85
ltc2978 13 2978fc typical performance characteristics supply current vs supply voltage supply current vs temperature v out_en[3:0] and v in_en output high voltage vs load current dac output impedance vs frequency v out_en[3:0] and v in_en v ol vs current v out_en[7:4] v ol vs current v dd33 (v) 3 supply current (ma) 10.0 10.1 10.2 3.3 3.5 2978 g28 9.9 9.8 3.1 3.2 3.4 10.3 10.4 10.5 3.6 v pwr = v dd33 temperature (c) ?50 10.02 supply current (ma) 10.04 10.08 10.10 10.12 10.16 ?35 25 55 2978 g29 10.06 10.14 10 85 100 ?20 ?5 40 70 v pwr = 12v frequency (khz) 0.01 output impedance () 10 100 1000 100 2978 g31 1 0.1 0.01 0.1 1 10 1000 i sink (ma) 0 1.4 1.2 1.0 0.8 85c ?40c 0.6 0.4 0.2 0 6 10 2978 g32 2 4 8 12 volts (v) 25c i sink (ma) 0 0 volts (v) 0.1 0.2 0.3 85c ?40c 0.4 0.6 4 8 12 16 2978 g33 20 24 0.5 25c current sourcing (a) 0 9.5 charge pump outupt high voltage (v) 10.0 11.0 11.5 12.0 4 14.0 2978 g30 10.5 2 1 5 6 3 7 12.5 13.0 13.5 85c 25c ?40c pwrgd and faultbz n v ol vs current alertb v ol vs current i sink (ma) 0 0 volts (v) 0.2 0.4 0.6 0.8 1.2 2 4 6 8 2978 g34 10 12 1.0 85c 25c ?40c i sink (ma) 0 1.4 1.2 1.0 0.8 85c ?40c 0.6 0.4 0.2 0 6 10 2978 g35 2 4 8 12 volts (v) 25c
ltc2978 14 2978fc pin functions pin name pin number pin type description v sensem6 1* in dc/dc converter differential (C) output voltage-6 sensing pin v sensep7 2* in dc/dc converter differential (+) output voltage or current-7 sensing pin v sensem7 3* in dc/dc converter differential (C) output voltage or current-7 sensing pin v out_en0 4 out dc/dc converter enable-0 pin. output high voltage optionally pulled up to 12v by 5a v out_en1 5 out dc/dc converter enable-1 pin. output high voltage optionally pulled up to 12v by 5a v out_en2 6 out dc/dc converter enable-2 pin. output high voltage optionally pulled up to 12v by 5a v out_en3 7 out dc/dc converter enable-3 pin. output high voltage optionally pulled up to 12v by 5a v out_en4 8 out dc/dc converter open-drain pull-down output-4 v out_en5 9 out dc/dc converter open-drain pull-down output-5 v out_en6 10 out dc/dc converter open-drain pull-down output-6 v out_en7 11 out dc/dc converter open-drain pull-down output-7 v in_en 12 0ut dc/dc converter v in enable pin. output high voltage optionally pulled up to 12v by 5a dnc 13 do not connect do not connect to this pin v in_sns 14 in v in sense input. this voltage is compared against the v in on and off voltage thresholds in order to determine when to enable and disable, respectively, the downstream dc/dc converters v pwr 15 in v pwr serves as the unregulated power supply input to the chip (4.5v to 15v). if a 4.5v to 15v supply voltage is unavailable, short v pwr to v dd33 and power the chip directly from a 3.3v supply. bypass to gnd with 0.1f capacitor. v dd33 16 in/out if shorted to v pwr , it serves as 3.13v to 3.47v supply input pin. otherwise it is a 3.3v internally regulated voltage output (use 100nf decoupling capacitor to gnd) v dd33 17 in input for internal 2.5v sub-regulator. short this pin to pin 16 v dd25 18 in/out 2.5v internally regulated voltage output. bypass to gnd with a 0.1f capacitor wp 19 in digital input. write-protect input pin, active high pwrgd 20 out power good open-drain output. indicates when outputs are power good. can be used as system power-on reset. the latency of this signal may be as long as the adc latency. see note 6. share_clk 21 in/out bidirectional clock sharing pin. connect a 5.49k pull-up resistor to v dd33 wdi/resetb 22 in watchdog timer interrupt and chip reset input. connect a 10k pull-up resistor to v dd33 . rising edge resets watchdog counter. holding this pin low for more than t resetb resets the chip faultb00 23 in/out open-drain output and digital input. active low bidirectional fault indicator-00. connect a 10k pull-up resistor to v dd33 faultb01 24 in/out open-drain output and digital input. active low bidirectional fault indicator-01. connect a 10k pull-up resistor to v dd33 faultb10 25 in/out open-drain output and digital input. active low bidirectional fault indicator-10. connect a 10k pull-up resistor to v dd33 faultb11 26 in/out open-drain output and digital input. active low bidirectional fault indicator-11. connect a 10k pull-up resistor to v dd33 sda 27 in/out pmbus bidirectional serial data pin scl 28 in pmbus serial clock input pin (400khz maximum) alertb 29 out open-drain output. generates an interrupt request in a fault/warning situation control0 30 in control pin 0 input control1 31 in control pin 1 input asel0 32 in ternary address select pin 0 input. connect to v dd33 , gnd or float to encode 1 of 3 logic states asel1 33 in ternary address select pin 1 input. connect to v dd33 , gnd or float to encode 1 of 3 logic states refp 34 out reference voltage output. needs 0.1f decoupling capacitor to refm refm 35 out reference return pin. needs 0.1f decoupling capacitor to refp. v sensep0 36* in dc/dc converter differential (+) output voltage-0 sensing pin v sensem0 37* in dc/dc converter differential (C) output voltage-0 sensing pin v dacm0 38 out dac0 return. connect to channel 0 dc/dc converters gnd sense or return to gnd v dacp0 39 out dac0 output v dacp1 40 out dac1 output
ltc2978 15 2978fc pin name pin number pin type description v dacm1 41 out dac1 return. connect to channel 1 dc/dc converters gnd sense or return to gnd v sensep1 42* in dc/dc converter differential (+) output voltage or current-1 sensing pins v sensem1 43* in dc/dc converter differential (C) output voltage or current-1 sensing pins v dacp2 44 out dac2 output v dacm2 45 out dac2 return. connect to channel 2 dc/dc converters gnd sense or return to gnd v sensep2 46* in dc/dc converter differential (+) output voltage-2 sensing pin v sensem2 47* in dc/dc converter differential (C) output voltage-2 sensing pin v sensep3 48* in dc/dc converter differential (+) output voltage or current-3 sensing pins v sensem3 49* in dc/dc converter differential (C) output voltage or current-3 sensing pins v dacp3 50 out dac3 output v dacm3 51 out dac3 return. connect to channel 3 dc/dc converters gnd sense or return to gnd v sensep4 52* in dc/dc converter differential (+) output voltage-4 sensing pin v sensem4 53* in dc/dc converter differential (C) output voltage-4 sensing pin v dacm4 54 out dac4 return. connect to channel 4 dc/dc converters gnd sense or return to gnd v dacp4 55 out dac4 output v dacp5 56 out dac5 output v dacm5 57 out dac5 return. connect to channel 5 dc/dc converters gnd sense or return to gnd v dacm6 58 out dac6 return. connect to channel 6 dc/dc converters gnd sense or return to gnd v dacp6 59 out dac6 output v dacp7 60 out dac7 output v dacm7 61 out dac7 return. connect to channel 7 dc/dc converters gnd sense or return to gnd v sensep5 62* in dc/dc converter differential (+) output voltage or current-5 sensing pins v sensem5 63* in dc/dc converter differential (C) output voltage or current-5 sensing pins v sensep6 64* in dc/dc converter differential (+) output voltage-6 sensing pin gnd 65 ground exposed pad, must be soldered to pcb *any unused v sensepn or v sensemn or v dacmn pins must be tied to gnd. pin functions
ltc2978 16 2978fc block diagram 15 3.3v regulator internal temp sensor reference 1.232v (typ) output config clock generation oscillator uvlo v dd open-drain output eeprom nonvolatile memory ram adc_results monitor limits servo targets pmbus interface (400khz i 2 c compatible) controller pmbus algorithm fault processor watchdog sequencer v in v dd v sensem0 v sensep0 v out v pwr 17 2.5v regulator v in v out v dd33 36 v sensep0 37 v sensem0 v sensep1 v sensem1 v sensep2 v sensem2 v sensep3 v sensem3 v sensep4 v sensem4 v sensep5 v sensem5 v sensep6 v sensem6 2 v sensep7 3 v sensem7 v dacp0 v dacp1 v dacp2 v dacp3 v dacp4 v dacp5 v dacp6 v dacp7 v dacm0 v dacm1 v dacm2 v dacm3 v dacm4 v dacm5 v dacm6 v dacm7 4 v out_en0 5 v out_en1 6 v out_en2 7 v out_en3 8 v out_en4 9 v out_en5 10 v out_en6 11 v out_en7 2978 bd 12 v in_en 18 v dd25 65 gnd 28 scl 27 sda 29 alertb 32 asel0 33 asel1 30 control0 19 wp 31 control1 wdi/resetb 22 23 faultb00 24 faultb01 25 faultb10 26 faultb11 20 21 share_clk pwrgd 16 v dd33 14 v in_sns refp refm 3r r v sensem1 v sensep1 v sensem2 v sensep2 v sensem3 v sensep3 v sensem4 v sensep4 v sensem5 v sensep5 v sensem6 v sensep6 v sensem7 v sensep7 16-bit ? adc adc clocks v dd + ? + ? mux 34 35 10-bit vdac + ? + + ? ? + ? sc cmp0 cmp0 vbuf0 dac0 10 bits 42 43 46 47 48 49 52 53 62 63 64 1 39 40 44 50 55 56 60 38 41 45 51 54 57 58 61 59
ltc2978 17 2978fc operation operation overview the ltc2978 is a pmbus programmable power supply controller, monitor, sequencer and voltage supervisor that can perform the following operations: n accept pmbus compatible programming commands. n provide dc/dc converter input voltage and output volt - age/current read back through the pmbus interface. n control the output of dc/dc converters that set the output voltage with a trim pin or dc/dc converters that set the output voltage using an external resistor feedback network. n sequence the start-up of dc/dc converters via pmbus programming and the control input pins. n trim the dc/dc converter output voltage (typically in 0.2% steps), in closed-loop servo operating mode, through pmbus programming. n margin the dc/dc converter output voltage to pmbus programmed limits. n allow the user to trim or margin the dc/dc converter output voltage in a manual operating mode by providing direct access to the margin dac. n supervise the dc/dc converter output voltage, input voltage, and the ltc2978 die temperature for over - value/undervalue conditions with respect to pmbus programmed limits and generate appropriate faults and warnings. n respond to a fault condition by either continuing op - eration indefnitely, latching off after a programmable deglitch period or latching off immediately. a retry mode may be used to automatically recover from a latched-off condition. n optionally stop trimming the dc/dc converter output voltage after it reached the initial margin or nominal target. optionally allow servo to resume if target drifts outside of v out warning limits. n store command register contents with crc to eeprom through pmbus programming. n restore eeprom contents through pmbus program - ming or when v dd33 is applied on power-up. n report the dc/dc converter output voltage status through the pmbus interface and the power good output. n generate interrupt requests by asserting the alertb pin in response to supported pmbus faults and warnings. n coordinate system wide fault responses for all dc/dc converters connected to the faultbz0 and faultbz1 pins. n synchronize sequencing delays or shutdown for multiple devices using the share_clk pin. n software and hardware write protect the command registers. n disable the input voltage to the supervised dc/dc converters in response to output voltage ov and uv faults. n log telemetry and status data to eeprom in response to a faulted-off condition n supervise an external microcontrollers activity for a stalled condition with a programmable watchdog timer and reset it if necessary. n prevent a dc/dc converter from re-entering the on state after a power cycle until a programmable interval (mfr_restart_delay) has elapsed and its output has decayed below a programmable threshold voltage (mfr_vout_discharge_threshold). n record minimum and maximum observed values of input voltage, output voltages and temperature. eeprom the ltc2978 contains internal eeprom (nonvolatile memory) to store confguration settings and fault log information. eeprom endurance, retention, and mass write operation time are specifed over the operating tem - perature range. see electrical characteristics and absolute maximum ratings sections.
ltc2978 18 2978fc operation nondestructive operation above t j = 85c is possible although the electrical characteristics are not guaranteed and the eeprom will be degraded. operating the eeprom above 85c may result in a deg - radation of retention characteristics. the fault logging function, which is useful in debugging system problems that may occur at high temperatures, only writes to fault log eeprom locations. if occasional writes to these reg - isters occur above 85c, a slight degradation in the data retention characteristics of the fault log may occur. it is recommended that the eeprom not be written using store_user_all or bulk programming when t j > 85c. the degradation in eeprom retention for temperatures >85c can be approximated by calculating the dimension - less acceleration factor using the following equation. af = e ea k ? ? ? ? ? ? ? 1 t use + 273 ? 1 t stress + 273 ? ? ? ? ? ? ? ? ? ? ? ? ? ? where: af = acceleration factor ea = activation energy = 1.4 ev k = 8.62510 ?5 ev/k t use = 85c specifed junction temperature t stress = actual junction temperature c example: calculate the effect on retention when operating at a junction temperature of 95c for 10 hours. t stress = 95c t use = 85c af = 3.4 equivalent operating time at 85c = 34 hours. so the overall retention of the eeprom was degraded by 34 hours as a result of operation at a junction temperature of 95c for 10 hours. note that the effect of this overstress is negligible when compared to the overall eeprom retention rating of 87,600 hours at a maximum junction temperature of 85c. reset holding the wdi/resetb pin low for more than t resetb will cause the ltc2978 to enter the power-on reset state. following the subsequent rising-edge of the wdi/resetb pin, the ltc2978 will execute its power-on sequence per the user confguration stored in eeprom. write-protect pin the wp pin allows the user to write-protect the ltc2978s confguration registers. the wp pin is active high, and when asserted it provides level 2 protection: all writes are disabled except to the write_protect, page, store_user_all, operation, mfr_page_ff_mask and clear_faults commands. the most restrictive set - ting between the wp pin and write_protect command will override. for example if wp = 1 and write_protect = 0x80, then the write_protect command overrides, since it is the most restrictive. other operations clock sharing multiple ltc pmbus devices can synchronize their clocks in an application by connecting together the open-drain share_clk input/outputs to a pull-up resistor as a wired or. in this case the fastest clock will take over and syn - chronize all ltc2978s. share_clk can optionally be used to synchronize on/off dependency on v in across multiple chips by setting bit 3 (mfr_confg_all_vin_share_enable) of the mfr_config_ all register. when confgured this way the chip will hold share_clk low when the unit is off for insuffcient input voltage and upon detecting that share_clk is held low the chip will disable all channels after a brief deglitch period. when the share_clk pin is allowed to rise, the chip will respond by beginning a soft-start requence. in this case the slowest vin_on detection will take over and synchronize other chips to its soft-start sequence.
ltc2978 19 2978fc pmbus serial digital interface the ltc2978 communicates with a host (master) using the standard pmbus serial bus interface. the pmbus timing diagram shows the timing relationship of the signals on the bus. the two bus lines, sda and scl, must be high when the bus is not in use. external pull-up resistors or current sources are required on these lines. the ltc2978 is a slave device. the master can communicate with the ltc2978 using the following formats: n master transmitter, slave receiver n master receiver, slave transmitter the following smbus protocols are supported: n write byte, write word, send byte n read byte, read word, block read n alert response address figures 1-12 illustrate the aforementioned smbus pro - tocols. all transactions support pec (parity error check) and gcp (group command protocol). the block read supports 255 bytes of returned data. for this reason, the pmbus timeout may be extended using the mfr_confg_all_ longer_pmbus_timeout setting. the ltc2978 will not acknowledge any pmbus command if it is still busy with a store_user_all, restore_ user_all, mfr_config_ltc2978 or if fault log data is being written to the eeprom. status_word_busy will also be set. pmbus pmbus is an industry standard that defnes a means of communication with power conversion devices. it is comprised of an industry standard smbus serial interface and the pmbus command language. the pmbus two wire interface is an incremental extension of the smbus. smbus is built upon i 2 c with some minor differences in timing, dc parameters and protocol. the smbus protocols are more robust than simple i 2 c byte commands because they provide timeouts to prevent bus hangs and optional packet error checking (pec) to ensure data integrity. in general, a master device that can be confgured for i 2 c communication can be used for pmbus communication with little or no change to hardware or frmware. for a description of the minor extensions and exceptions pmbus makes to smbus, refer to pmbus specifcation part 1 revision 1.1: paragraph 5: transport. this can be found at: www.pmbus.org . for a description of the differences between smbus and i 2 c, refer to system management bus (smbus) specifca - tion version 2.0: appendix b C differences between smbus and i 2 c. this can be found at: www.smbus.org . when using an i 2 c controller to communicate with a pmbus part it is important that the controller be able to write a byte of data without generating a stop. this will allow the controller to properly form the repeated start of the pmbus read command by concatenating a start command byte write with an i 2 c read. operation
ltc2978 20 2978fc slave address command code data byte low wr a a a p 2978 f02 s 7 8 8 1 data byte high 8 1 1 1 1 1 1 a slave address command code data byte wr a a a p 2978 f03 s 7 8 8 1 pec 8 1 1 1 1 1 1 a slave address command code data byte low wr a a a p 2978 f04 s 7 8 8 1 data byte high 8 pec 8 1 1 1 1 1 1 1 a a figure 1b. write byte protocol figure 2. write word protocol figure 3. write byte protocol with pec figure 4. write word protocol with pec operation slave address wr a a p 2978 f05 s 7 8 1 1 1 1 1 command code slave address command code pec wr a a a p 2978 f06 s 7 8 8 1 1 1 1 1 1 figure 5. send byte protocol figure 6. send byte protocol with pec figure 1a. pmbus packet protocol diagram element key slave address command code data byte wr a a a p 2978 f01b s 7 8 8 1 1 1 1 1 1 slave address command code wr a a p 2978 f01a s 7 8 1 1 1 1 1 s sr rd wr x a p pec start condition repeated start condition read (bit value of 1) write (bit value of 0) shown under a field indicates that the field is required to have the value of x acknowledge (this bit position may be 0 for an ack or 1 for a nack) stop condition packet error code master to slave slave to master continuation of protocol ... x x
ltc2978 21 2978fc operation figure 10. read byte protocol with pec 2978 f11 slave address command code sr wr a a s 7 8 7 11 byte count = n 8 1 ... 1 1 1 1 a a 1 slave address rd data byte 1 data byte 2 a a ... ... 8 8 8 11 1 1 1 a data byte n p 2978 f12 slave address command code sr wr a a s 7 8 7 11 byte count = n 8 1 ... 1 1 1 1 a a 1 slave address rd data byte 1 data byte 2 a a ... ... 8 8 8 8 1 1 1 1 1 1 a a p data byte n pec figure 11. block read figure 12. block read with pec slave address command code slave address wr a a a p 2978 f07 s 7 8 7 1 data byte low 8 data byte high 8 1 1 1 1 s 1 1 1 1 1 a 1 rd a slave address command code slave address wr a a a pa 2978 f08 s 7 8 7 1 data byte low 8 data byte high pec 8 8 1 1 1 1 1 1 11 1 s 1 a 1 rd a figure 7. read word protocol figure 8. read word protocol with pec figure 9. read byte protocol slave address command code slave address wr a a s p 2978 f09 s 7 8 7 11 data byte 8 1 1 1 1 1 1 1 1 a rd a slave address command code slave address wr a a s p 2978 f10 s 7 8 7 11 data byte 8 1 1 1 1 1 1 1 1 a rd a 1 a pec
ltc2978 22 2978fc device address the i 2 c/smbus address of the ltc2978 equals the base address + n where n is a number from 0 to 8. n can be confgured by setting the asel0 and asel1 pins to v dd33 , gnd or float. see table 1. using one base address and the nine values of n, nine ltc2978s can be connected together to control 72 outputs. the base address is stored in the mfr_i2c_base_address register. the base address can be written to any value, but generally should not be table 1. ltc2978 device address look-up table address description hex device address binary device address bits address pins 7-bit 8-bit 6 5 4 3 2 1 0 r/w asel1 asel0 alert response 0c 19 0 0 0 1 1 0 0 1 x x global 5b b6 1 0 1 1 0 1 1 0 x x n = 0 5c* b8 1 0 1 1 1 0 0 0 l l n = 1 5d ba 1 0 1 1 1 0 1 0 l nc n = 2 5e bc 1 0 1 1 1 1 0 0 l h n = 3 5f be 1 0 1 1 1 1 1 0 nc l n = 4 60 c0 1 1 0 0 0 0 0 0 nc nc n = 5 61 c2 1 1 0 0 0 0 1 0 nc h n = 6 62 c4 1 1 0 0 0 1 0 0 h l n = 7 63 c6 1 1 0 0 0 1 1 0 h nc n = 8 64 c8 1 1 0 0 1 0 0 0 h h h = tie to v dd33 , nc = no connect = open or float, l = tie to gnd, x = dont care *mfr_i2c_base_address = 7bit 5c (factory default) changed unless the desired range of addresses overlap existing addresses. watch that the address range does not overlap with other i 2 c/smbus device or global addresses, including i 2 c/smbus multiplexers and bus buffers. this will bring you great happiness. the ltc2978 always responds to its global address and the smbus alert response address regardless of the state of its asel pins and the mfr_i2c_base_address register . operation
ltc2978 23 2978fc processing commands the ltc2978 uses a dedicated processing block to ensure quick response to all of its commands. there are a few exceptions where the part will nack a subsequent command because it is still processing the previous command. these are summarized in the following tables. eeprom related commands command typical delay* comment store_user_all mass_write see electrical characterization table. the ltc2978 will not accept any commands while it is transferring register contents to the eeprom. the command byte will be nacked. restore_user_all 30ms the ltc2978 will not accept any commands while it is transferring eeprom data to command registers. the command byte will be nacked. mfr_data_log_clear 175ms the ltc2978 will not accept any commands while it is initializing the fault log eeprom space. the command byte will be nacked. mfr_data_log_store 20ms the ltc2978 will not accept any commands while it is transferring the fault log ram buffer to eeprom space. the command byte will be nacked. internal fault log 10ms an internal fault log event is a one time event that uploads the contents of the fault log to eeprom in response to a fault. internal fault logging may be disabled. commands received during this eeprom write are nacked. mfr_data_log_ restore 2ms the ltc2978 will not accept any commands while it is transferring eeprom data to the fault log ram buffer. the command byte will be nacked. *the typical delay is measured from the commands stop to the next commands start. command typical delay* comment mfr_config_ltc2978 <50s the ltc2978 will not accept any commands while it is completing this command. the command byte will be nacked. *the delay is measured from the commands stop to the next commands start. other pmbus timing notes command comment clear_faults the ltc2978 will accept commands while it is completing this command but the affected status fags will not be cleared for up to 500s. operation
ltc2978 24 2978fc summary table command name cmd code description type paged d ata format units nvm default value float hex ref page page 0x00 channel or page currently selected for any command that supports paging. r/w byte n reg 0x00 29 operation 0x01 operating mode control. on/off, margin high and margin low. r/w byte y reg y 0x00 30 on_off_config 0x02 control pin & pmbus bus on/off command setting. r/w byte y reg y 0x12 31 clear_faults 0x03 clear any fault bits that have been set. send byte y na 31 write_protect 0x10 level of protection provided by the device against accidental changes. r/w byte n reg y 0x00 32 store_user_all 0x15 store entire operating memory to eeprom. send byte n na 32 restore_user_all 0x16 restore entire operating memory from eeprom. send byte n na 32 capability 0x19 summary of pmbus optional communication protocols supported by this device. r byte n reg 0xe0 32 vout_mode 0x20 output voltage data format and mantissa exponent. (2 C13 ) r byte y reg 0x13 33 vout_command 0x21 servo target. nominal dc/dc converter output voltage setpoint. r/w word y l16 v y 1.0 0x2000 33 vout_max 0x24 upper limit on the output voltage the unit can command regardless of any other commands. r/w word y l16 v y 4.0 0x8000 33 vout_margin_high 0x25 margin high dc/dc converter output voltage setting. r/w word y l16 v y 1.05 0x219a 33 vout_margin_low 0x26 margin low dc/dc converter output voltage setting. r/w word y l16 v y 0.95 0x1e66 33 vin_on 0x35 input voltage above which power conversion can be enabled. r/w word n l11 v y 10.0 0xd280 33 vin_off 0x36 input voltage below which power conversion is disabled. all v out_en pins go off immediately. r/w word n l11 v y 9.0 0xd240 33 vout_ov_fault_limit 0x40 output overvoltage fault limit r/w word y l16 v y 1.1 0x2333 33 vout_ov_fault_ response 0x41 action to be taken by the device when an output overvoltage fault is detected. r/w byte y reg y 0x80 35 vout_ov_warn_limit 0x42 output overvoltage warning limit . r/w word y l16 v y 1.075 0x2266 33 vout_uv_warn_limit 0x43 output undervoltage warning limit r/w word y l16 v y 0.925 0x1d9a 33 vout_uv_fault_limit 0x44 output undervoltage fault limit. limit used to determine if ton_max_fault has been met and the unit is on. r/w word y l16 v y 0.9 0x1ccd 33 vout_uv_fault_ response 0x45 action to be taken by the device when an output undervoltage fault is detected. r/w byte y reg y 0x7f 35 ot_fault_limit 0x4f overtemperature fault limit setting. r/w word n l11 c y 85.0 0xeaa8 34 pmbus command summary
ltc2978 25 2978fc summary table command name cmd code description type paged d ata format units nvm default value float hex ref page ot_fault_response 0x50 action to be taken by the device when an overtemperature fault is detected. r/w byte n reg y 0xb8 36 ot_warn_limit 0x51 overtemperature warning limit setting. r/w word n l11 c y 75.0 0xea58 34 ut_warn_limit 0x52 undertemperature warning limit. r/w word n l11 c y 0 0x8000 34 ut_fault_limit 0x53 undertemperature fault limit. r/w word n l11 c y C5.0 0xcd80 34 ut_fault_response 0x54 action to be taken by the device when an undertemperature fault is detected. r/w byte n reg y 0xb8 36 vin_ov_fault_limit 0x55 input overvoltage fault limit measured at v in_sns pin r/w word n l11 v y 15.0 0xd3c0 33 vin_ov_fault_response 0x56 action to be taken by the device when an input overvoltage fault is detected. r/w byte n reg y 0x80 36 vin_ov_warn_limit 0x57 input overvoltage warning limit measured at v in_sns pin r/w word n l11 v y 14.0 0xd380 33 vin_uv_warn_limit 0x58 input undervoltage warning limit measured at v in_sns pin. r/w word n l11 v y 0 0x8000 33 vin_uv_fault_limit 0x59 input undervoltage fault limit measured at v in_sns pin r/w word n l11 v y 0 0x8000 33 vin_uv_fault_response 0x5a action to be taken by the device when an input undervoltage fault is detected. r/w byte n reg y 0x00 36 power_good_on 0x5e output voltage at or above which a power good should be asserted. r/w word y l16 v y 0.96 0x1eb8 33 power_good_off 0x5f output voltage at or below which a power good should be deasserted. r/w word y l16 v y 0.94 0x1e14 33 ton_delay 0x60 time from control pin and/or operation command = on to v out_en pin = on. r/w word y l11 ms y 1.0 0xba00 34 ton_rise 0x61 time from when the output starts to rise until the ltc2978 optionally soft-connects its dac and begins to servo the output voltage to the desired value. r/w word y l11 ms y 10.0 0xd280 34 ton_max_fault_limit 0x62 maximum time from v out_en = on assertion that an uv condition will be tolerated before a ton_max_fault condition results. r/w word y l11 ms y 15.0 0xd3c0 34 ton_max_fault_ response 0x63 action to be taken by the device when a ton_max_fault event is detected. r/w byte y reg y 0xb8 36 toff_delay 0x64 time from control pin and/or operation command = off to v out_en pin = off. r/w word y l11 ms y 1.0 0xba00 34 status_byte 0x78 one byte summary of the unit's fault condition. r byte y reg na 37 status_word 0x79 two byte summary of the unit's fault condition. r word y reg na 38 status_vout 0x7a output voltage fault and warning status. r byte y reg na 38 pmbus command summary
ltc2978 26 2978fc pmbus command summary summary table command name cmd code description type paged d ata format units nvm default value float hex ref page status_input 0x7c input voltage fault and warning status measured at vin_sns pin. r byte n reg na 39 status_temperature 0x7d temperature fault and warning status for read_temperature_1. r byte n reg na 39 status_cml 0x7e communication and memory fault and warning status. r byte n reg na 40 status_mfr_specific 0x80 manufacturer specifc fault and state information. r byte y reg na 40 read_vin 0x88 input voltage measured at vin_sns pin.. r word n l11 v na 41 read_vout 0x8b dc/dc converter output voltage. r word y l16 v na 41 read_temperature_1 0x8d internal junction temperature. r word n l11 c na 41 pmbus_revision 0x98 pmbus revision supported by this device. current revision is 1.1. r byte n reg 0x11 41 mfr_config_ltc2978 0xd0 confguration bits that are channel specifc. r/w word y reg y 0x0080 42 mfr_config_all_ ltc2978 0xd1 confguration bits that are common to all pages. r/w byte n reg y 0x7b 43 mfr_faultbz0_ propagate 0xd2 confguration that determines if a channels faulted off state is propagated to the faultb00 and faultb10 pins. r/w byte y reg y 0x00 44 mfr_faultbz1_ propagate 0xd3 manufacturer confguration that confguration that determines if a channels faulted off state is propagated to the faultb01 and faultb11 pins. r/w byte y reg y 0x00 44 mfr_pwrgd_en 0xd4 confguration for mapping pwrgd and wdi/resetb status to the pwrgd pin. r/w word n reg y 0x0000 45 mfr_faultb00_ response 0xd5 action to be taken by the device when the faultb00 pin is asserted low. r/w byte n reg y 0x00 46 mfr_faultb01_ response 0xd6 action to be taken by the device when the faultb01 pin is asserted low. r/w byte n reg y 0x00 46 mfr_faultb10_ response 0xd7 action to be taken by the device when the faultb10 pin is asserted low. r/w byte n reg y 0x00 46 mfr_faultb11_ response 0xd8 action to be taken by the device when the faultb11 pin is asserted low. r/w byte n reg y 0x00 46 mfr_vinen_ov_fault_ response 0xd9 action to be taken by the v in_en pin in response to a vout_ov_fault r/w byte n reg y 0x00 47 mfr_vinen_uv_fault_ response 0xda action to be taken by the v in_en pin in response to a vout_uv_fault r/w byte n reg y 0x00 48 mfr_retry_delay 0xdb retry interval during fault retry mode. r/w word n l11 ms y 200.0 0xf320 48 mfr_restart_delay 0xdc delay from actual control active edge to virtual control active edge. r/w word n l11 ms y 400.0 0xfb20 49 mfr_vout_peak 0xdd maximum measured value of read_ vout. r word y l16 v na 49 mfr_vin_peak 0xde maximum measured value of read_vin. r word n l11 v na 49
ltc2978 27 2978fc summary table command name cmd code description type paged d ata format units nvm default value float hex ref page mfr_temperature_ peak 0xdf maximum measured value of read_ temperature_1. r word n l11 c na 49 mfr_dac 0xe0 manufacturer register that contains the code of the 10-bit dac. r/w word y u16 y 0x0000 50 mfr_powergood_ assertion_delay 0xe1 power good output assertion delay. r/w word n l11 ms y 100.0 0xeb20 50 mfr_watchdog_t_first 0xe2 first watchdog timer interval. r/w word n l11 ms y 0 0x8000 50 mfr_watchdog_t 0xe3 watchdog timer interval. r/w word n l11 ms y 0 0x8000 50 mfr_page_ff_mask 0xe4 confguration defning which channels respond to global page commands (page=0xff). r/w byte n reg y 0xff 51 mfr_pads 0xe5 current state of selected digital i/o pads. r word n reg n/a 52 mfr_i2c_base_address 0xe6 base value of the i 2 c/smbus address byte. r/w byte n u16 y 0x5c 52 mfr_special_id 0xe7 manufacturer code for identifying the ltc2978 r word n reg y 0x0121 52 mfr_special_lot 0xe8 customer dependent codes that identify the factory programmed user confguration stored in eeprom. contact factory for default value. r byte y reg y 53 mfr_vout_discharge_ threshold 0xe9 coeffcient used to multiply vout_ command in order to determine v out off threshold voltage. r/w word y l11 y 2.0 0xc200 53 mfr_fault_log_store 0xea command a transfer of the fault log from ram to eeprom. this causes the part to behave as if a channel has faulted off. send byte n na 55 mfr_fault_log_ restore 0xeb command a transfer of the fault log previously stored in eeprom back to ram. send byte n na 55 mfr_fault_log_clear 0xec initialize the eeprom block reserved for fault logging and clear any previous fault logging locks. send byte n na 55 mfr_fault_log_status 0xed fault logging status. r byte n reg y na 55 mfr_fault_log 0xee fault log data bytes. this sequentially retrieved data is used to assemble a complete fault log. 256 bytes. r block n reg y na 56 mfr_common 0xef manufacturer status bits that are common across multiple ltc chips. r byte n reg na 53 mfr_spare_0 0xf7 scratchpad register r/w word n reg y 0x0000 53 mfr_spare_2 0xf9 paged scratchpad register r/w word y reg y 0x0000 53 mfr_vout_min 0xfb minimum measured value of read_vout. r word y l16 v na 54 mfr_vin_min 0xfc minimum measured value of read_vin. r word n l11 v na 54 mfr_temperature_min 0xfd minimum measured value of read_ temperature_1. r word n l11 c na 54 pmbus command summary
ltc2978 28 2978fc data formats l11 linear_5s_11s pmbus data feld b[15:0] value = y ? 2 n where n = b[15:11] is a 5-bit twos complement integer and y = b[10:0] is an 11-bit twos complement integer example: read_vin = 10v for b[15:0] = 0xd280 = 1101_0010_1000_0000b value = 640 ? 2 C6 = 10 see pmbus spec part ii: paragraph 7.1 l16 linear_16u pmbus data feld b[15:0] value = y ? 2 n where y = b[15:0] is an unsigned integer and n = vout_mode_parameter is a 5-bit twos complement exponent that is hardwired to C13 decimal. example: vout_command = 4.75v for b[15:0] = 0x9800 = 1001_1000_0000_0000b value = 38912 ? 2 C13 = 4.75 see pmbus spec part ii: paragraph 8.3.1 reg register pmbus data feld b[15:0] or b[7:0]. bit feld meaning is defned in detailed pmbus command register description. u16 integer word pmbus data feld b[15:0] value = y where y = b[15:0] is a 16-bit unsigned integer example: for b[15:0] = 0x9807 = 1001_1000_0000_0111b value = 38919 cf custom format pmbus data feld b[15:0] value is defned in detailed pmbus command register description. this is often an unsigned or twos complement integer scaled by an mfr specifc constant. pmbus command summary
ltc2978 29 2978fc operation, mode and eeprom commands page the ltc2978 has eight pages that correspond to the eight dc/dc converter channels that can be managed. each dc/dc converter channel can be uniquely programmed by frst setting the appropriate page. the page command provides the ability to confgure, control and monitor multiple outputs on one unit. setting page = 0xff allows a simultaneous write to all pages for pmbus commands that support global page program - ming. the only commands that support page = 0xff are operation and on_off_config. see mfr_page_ff_mask for additional options. reading any paged pmbus register with page = 0xff returns unpredictable data and will trigger a cml fault. page data contents bit(s) symbol purpose b[7:0] page page operation. 0x00: all pmbus commands address channel/page 0. 0x01: all pmbus commands address channel/page 1. ? ? ? 0x07: all pmbus commands address channel/page 7. 0xxx: all nonspecifed values reserved. 0xff: a single pmbus write/send to commands that support this mode will simultaneously address all channels/pages with mfr_page_ff_mask enabled. pmbus command description
ltc2978 30 2978fc pmbus command description operation the operation command is used to turn the unit on and off in conjunction with the control n pin and on_off_con - fig. this command register responds to the global page command (page=0xff). the contents and functions of the data byte are shown in the following tables. operation data contents (on_off_confg_use_pmbus=1) symbol action operation_control[1:0] operation_margin[1:0] operation_fault[1:0] reserved (read only) bits b[7:6] b[5:4] b[3:2] b[1:0] function turn off immediately 00 xx xx 00 turn on 10 00 xx 00 margin low (ignore faults and warnings) 10 01 01 00 margin low 10 01 10 00 margin high (ignore faults and warnings 10 10 01 00 margin high 10 10 10 00 sequence off and margin to nominal 01 00 xx 00 sequence off and margin low (ignore faults and warnings) 01 01 01 00 sequence off and margin low 01 01 10 00 sequence off and margin high (ignore faults and warnings) 01 10 01 00 sequence off and margin high 01 10 10 00 reserved all remaining combinations operation data contents (on_off_confg_use_pmbus=0) symbol action operation_control[1:0] operation_margin[1:0] operation_fault[1:0] reserved (read only) bits b[7:6] b[5:4] b[3:2] b[1:0] function output at nominal 00, 01 or 10 00 xx 00 margin low (ignore faults and warnings) 00, 01 or 10 01 01 00 margin low 00, 01 or 10 01 10 00 margin high (ignore faults and warnings 00, 01 or 10 10 01 00 margin high 00, 01 or 10 10 10 00 reserved all remaining combinations
ltc2978 31 2978fc on_off_config the on_off_config command confgures the combination of control n pin input and pmbus bus commands needed to turn the ltc2978 on/off, including the power-on behavior, as shown in the following table. this command register responds to the global page command (page=0xff). after the part has initialized, an additional comparator monitors vin_sns. the vin_on threshold must be exceeded before the output power sequencing can begin. after v in is initially applied, the part will typically require 135ms to initialize and begin the ton_delay timer. the readback of voltages and currents may require an additional 160ms. on_off_config data contents bits(s) symbol operation b[7:5] reserved dont care. always returns 0. b[4] on_off_confg_controlled_on controls default autonomous power-up operation. 0: unit powers up regardless of the controln pin or operation value. unit always powers up with sequencing. to turn unit on without sequencing, set ton_delay = 0. 1: unit does not power up unless commanded by the controln pin and/or the operation command on the serial bus. if on_off_confg[3:2] = 00, the unit never powers up. b[3] on_off_confg_use_pmbus controls how the unit responds to commands received via the serial bus. 0: unit ignores the operation_control[1:0] bits. 1: unit responds to operation_control[1:0]. depending on on_off_confg_use_control, the unit may also require the controln pin to be asserted for the unit to start. b[2] on_off_confg_use_control controls how unit responds to the controln pin. 0: unit ignores the controln pin. 1: unit requires the controln pin to be asserted to start the unit. depending on on_off_confg_use_ pmbus the operation command may also be required to instruct the device to start. b[1] reserved not supported. always returns 1. b[0] on_off_confg_control_fast_off controln pin turn off action when commanding the unit to turn off 0: use the programmed toff_delay. 1: turn off the output and stop transferring energy as quickly as possible, i.e. pull v outenn low immediately. c lea r _ fa u lts the clear_faults command is used to clear any status faults that have been set. this command clears all bits in all unpaged status registers, and the paged status registers selected by the current page setting. at the same time, the device negates (clears, releases) its contribution to alertb. the clear_faults command does not cause a unit that has latched off for a fault condition to restart. see clearing latched faults for more information. if the fault condition is present after the fault status is cleared, the fault status bit shall be set again and the host noti - fed by the usual means. note: this command register does not respond to the global page command (page=0xff). pmbus command description
ltc2978 32 2978fc write_protect the write_protect command provides protection against accidental programming of the ltc2978 command reg - isters. all supported commands may have their parameters read, regardless of the write_protect setting. there are two levels of write protection: ? level 1: nothing can be changed except the level of write protection itself. values can be read from all pages. this setting can be stored to eeprom. ? level 2: nothing can be changed except for the level of protection, channel on/off state and clearing of faults. values can be read from all pages. this setting can be stored to eeprom. write_protect data contents bits(s) symbol operation b[7:0] write_protect[7:0] level 1: 1000_0000b: disable all writes except to the write_protect, page, and store_user_all commands. level 2: 0100_0000b: disable all writes except to the write_protect, page, store_user_all, operation, mfr_ page_ff_mask, and clear_faults. 0000_0000b: enable writes to all commands. xxxx_xxxxb: all other values reserved. store_user_all and restore_user_all store_user_all, restore_user_all commands provide access to user eeprom space. once a command is stored in user eeprom, it will be restored with an explicit restore command or when the part emerges from power- on reset after power is applied. while either of these commands is being processed, the device will nack i 2 c writes. store_user_all. issuing this command will store all operating memory commands with a corresponding eeprom memory location. it is recommended that this command not be executed while a unit is enabled since all monitoring is suspended while the operating memory is transferred to eeprom. restore_user_all. issuing this command will restore all commands from eeprom memory. it is recommended that this command not be executed while a unit is enabled since all monitoring is suspended while the eeprom is transferred to operating memory, and intermediate values from eeprom may not be compatible with the values initially stored in operating memory. capability the capability command provides a way for a host system to determine some key capabilities of the ltc2978. this one byte command is read only. capability data contents bits(s) symbol operation b[7] capability_pec hard coded to 1 indicating packet error checking is supported. reading the mfr_confg_all_pec_en bit will indicate whether pec is currently required. b[6] capability_scl_max hard coded to 1 indicating the maximum supported bus speed is 400khz. b[5] capability_smb_alert hard coded to 1 indicating this device does have an alertb pin and does support the smbus alert response protocol. b[4:0] reserved always returns 0. pmbus command description
ltc2978 33 2978fc vout_mode this command is read only and specifes the mode and exponent for all commands with a l16 data format. see data formats table on page 28. vout_mode data contents bit(s) symbol operation b[7:5] vout_mode_type reports linear mode. hard wired to 000b. b[4:0] vout_mode_parameter linear mode exponent. 5-bit twos complement integer. hardwired to 0x13 (C13 decimal). output voltage related commands vout_command, vout_max, vout_margin_high, vout_margin_low, vout_ov_fault_limit, vout_ov_ warn_limit, vout_uv_warn_limit, vout_uv_fault_limit, power_good_on and power_good_off these commands all use the same format and provide various servo, margining, and supervising limits for a chan - nels output voltage. when odd channels are confgured to measure current, the ov_warn_limit, uv_warn_limit, ov_fault_limit and uv_fault_limit commands are not supported. data contents bit(s) symbol operation b[15:0] vout_command[15:0], vout_max[15:0], vout_margin_high[15:0], vout_margin_low[15:0], vout_ov_fault_limit[15:0], vout_ov_warn_limit[15:0], vout_uv_warn_limit[15:0], vout_uv_fault_limit[15:0], power_good_on[15:0], power_good_off[15:0] these commands relate to output voltage. the data uses the l16 format. units: v input voltage related commands vin_on, vin_off, vin_ov_fault_limit, vin_ov_warn_limit, vin_uv_warn_limit and vin_uv_fault_ limit these commands use the same format and provide voltage supervising limits for v in . data contents bit(s) symbol operation b[15:0] vin_on[15:0], vin_off[15:0], vin_ov_fault_limit[15:0], vin_ov_warn_limit[15:0], vin_uv_warn_limit[15:0], vin_uv_fault_limit[15:0] these commands relate to input voltage. the data uses the l11 format. units: v. pmbus command description
ltc2978 34 2978fc temperature related commands ot_fault_limit, ot_warn_limit, ut_warn_limit and ut_fault_limit these commands provide supervising limits for temperature. data contents bit(s) symbol operation b[15:0] ot_fault_limit[15:0], ot_warn_limit[15:0], ut_warn_limit[15:0], ut_fault_limit[15:0] the data uses the l11 format. units: c. timer limits ton_delay, ton_rise, ton_max_fault_limit and toff_delay these commands share the same format and provide sequencing and timer fault and warning delays in ms. ton_delay is the amount time in ms that elapses after the channel has been allowed on (usually due to control n pin or operation command) until the channel enables the power supply. this delay is counted using share_clk only. ton_rise is the amount of time in ms that elapses after the power supply has been enabled until the ltc2978s dac soft connects and servos the output voltage to the desired level if mfr_dac_mode = 00b. this delay is counted using share_clk only. ton_max_fault_limit is the maximum amount of time that the power supply being controlled by the ltc2978 can attempt to power up the output without reaching the vout_uv_fault_limit. if the output reaches vout_uv_fault_ limit prior to ton_max_fault_limit, the ltc2978 unmasks the vout_uv_fault_limit threshold. if it does not, then a ton_max_fault is declared. (note that a value of zero means there is no limit to how long the power supply can attempt to bring up its output voltage.) this delay is counted using share_clk only. toff_delay is the amount of time that elapses after the control n pin and/or operation command is deasserted until the channel is disabled (soft-off). this delay is counted using share_clk if available, otherwise the internal oscillator is used. data contents bit(s) symbol operation b[15:0] ton_delay[15:0], ton_rise[15:0], ton_max_fault_limit[15:0], toff_delay[15:0], the data uses the l11 format. the internal timers operate on a 10s internal clock. the share_clk pin may be used to synchronize the 10s timer. delays are rounded to the nearest 10s units: ms. max value: 655ms pmbus command description
ltc2978 35 2978fc fault response for voltages measured by the high speed supervisor vout_ov_fault_response and vout_uv_fault_response the fault response documented here is for voltages that are measured by the high speed supervisor. these voltages are measured over a short period of time and may require a deglitch period. note that in addition to the response described by these commands, the ltc2978 will also: ? set the appropriate bit(s) in the status_byte ? set the appropriate bit(s) in the status_word ? set the appropriate bit in the corresponding status_vout register, and ? notify the host by pulling the alertb pin low. note: odd numbered channels confgured for high resolution adc measurements (for current measurement) will not respond to ov/uv faults or warnings. data contents bit(s) symbol operation b[7:6] vout_ov_fault_response_action, vout_uv_fault_response_action response action: 00b: the unit continues operation without interruption. 01b: the unit continues operating for the delay time specifed by bits[2:0] in increments of ts_vs. (see electrical characteristics table, voltage supervisor characteristics section). if the fault is still present at the end of the delay time, the unit shuts down and responds as programmed in the retry setting (bits [5:3]). 1xb: the device shuts down and responds according to the retry setting in bits [5:3]. b[5:3] vout_ov_fault_response_retry, vout_uv_fault_response_retry response retry behavior: 000b: a zero value for the retry setting means that the unit does not attempt to restart. the output remains disabled until the fault is cleared. 001b-111b: the pmbus device attempts to restart continuously, without limitation, at intervals of mfr_retry_ delay, until it is commanded off (by the control pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. b[2:0] vout_ov_fault_response_delay, vout_uv_fault_response_delay this sample count determines the amount of time a unit is to ignore a fault after it is frst detected. use this delay to deglitch fast faults. 000b: the unit turns off immediately. 001b-111b: the unit turns off after b[2:0] samples at the sampling period of ts_vs (12.2s typical). pmbus command description
ltc2978 36 2978fc fault response for values measured by the adc ot_fault_response, ut_fault_response, vin_ov_fault_response and vin_uv_fault_response the fault response documented here is for values that are measured by the adc. these values are measured over a longer period of time and are not deglitched. note that in addition to the response described by these commands, the ltc2978 will also: ? set the appropriate bit(s) in the status_byte ? set the appropriate bit(s) in the status_word ? set the appropriate bit in the corresponding status_vin or status_temperature register, and ? notify the host by pulling the alertb pin low. data contents bit(s) symbol operation b[7:6] ot_fault_response_action, ut_fault_response_action, vin_ov_fault_response_action, vin_uv_fault_response_action response action: 00b: the unit continues operation without interruption. 01b to 11b: the device shuts down and responds according to the retry setting in bits [5:3]. b[5:3] ot_fault_response_retry, ut_fault_response_retry, vin_ov_fault_response_retry, vin_uv_fault_response_retry response retry behavior: 000b: a zero value for the retry setting means that the unit does not attempt to restart. the output remains disabled until the fault is cleared. 001b-111b: the pmbus device attempts to restart continuously, without limitation, using mfr_retry_delay, until it is commanded off (by the controln pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. b[2:0] ot_fault_response_delay, ut_fault_response_delay, vin_ov_fault_response_delay, vin_uv_fault_response_delay hard coded to 000b. the unit turns off immediately. timed fault response ton_max_fault_response this command defnes the ltc2978 response to a ton_max_fault. it may be used to protect against a short-circuited output at start-up. after start-up use vout_uv_fault_response to protect against a short-circuited output. the device also: ? sets the high_byte bit in the status_byte, ? sets the vout bit in the status_word, ? sets the ton_max_fault bit in the status_vout register, and ? notifes the host by asserting alertb. pmbus command description
ltc2978 37 2978fc ton_max_fault_response data contents bit(s) symbol operation b[7:6] ton_max_fault_response_action response action: 00b: the unit continues operation without interruption. 01b: the unit continues operating for the delay time specifed which for this type of fault corresponds to an immediate shutdown. after shutting off, the device responds according to the retry settings in bits [5:3]. 1xb: the device shuts down and responds according to the retry setting in bits [5:3]. b[5:3] ton_max_fault_response_retry response retry behavior: 000b: a zero value for the retry setting means that the unit does not attempt to restart. the output remains disabled until the fault is cleared. 001b-111b: the pmbus device attempts to restart continuously, without limitation, using mfr_retry_delay, until it is commanded off (by the controln pin or operation command or both), bias power is removed, or another fault condition causes the unit to shut down. b[2:0] ton_max_fault_response_delay hard coded to 000b. the unit turns off immediately. clearing latched faults latched faults are reset by toggling the control pin, using the operation command, or removing and reapplying the bias voltage to the v in_sns pin. all fault and warning conditions result in the alertb pin being asserted low and the corresponding bits being set in the status registers. the clear_faults command resets the contents of the status registers and de-asserts the alertb output, but it does not clear a faulted off state nor allow a channel to turn back on. status commands status_byte: the status_byte command returns the summary of the most critical faults or warnings which have occurred, as shown in the following table. status_byte is a subset of status_word and duplicates the same information. status_byte data contents bit(s) symbol operation b[7] status_byte_busy same as status_word_busy b[6] status_byte_off same as status_word_off b[5] status_byte_vout_ov same as status_word_vout_ov b[4] status_byte_iout_oc same as status_word_iout_oc b[3] status_byte_vin_uv same as status_word_vin_uv b[2] status_byte_temp same as status_word_temp b[1] status_byte_cml same as status_word_cml b[0] status_byte_high_byte same as status_word_high_byte pmbus command description
ltc2978 38 2978fc status_word: the status_word command returns two bytes of information with a summary of the units fault condition. based on the information in these bytes, the host can get more information by reading detailed status register. the low byte of the status_word is the same register as the status_byte command. status_word data contents bit(s) symbol operation b[15] status_word_vout an output voltage fault or warning has occurred. see status_vout. b[14] status_word_iout not supported. always returns 0. b[13] status_word_input an input voltage fault or warning has occurred. see status_input. b[12] status_word_mfr a manufacturer specifc fault has occurred. see status_mfr_specific. b[11] status_word_power_not_good the power_good signal, if present is negated. power is not good. b[10] status_word_fans not supported. always returns 0. b[9] status_word_other not supported. always returns 0. b[8] status_word_unknown not supported. always returns 0. b[7] status_word_busy device busy when pmbus command received. see operation: processing commands. b[6] status_word_off this bit is asserted if the unit is not providing power to the output, regardless of the reason, including simply not being enabled. the off bit is clear if unit is allowed to provide power to the output. b[5] status_word_vout_ov an output overvoltage fault has occured. b[4] status_word_iout_oc not supported. always returns 0. b[3] status_word_vin_uv a v in undervoltage fault has occurred. b[2] status_word_temp a temperature fault or warning has occurred. see status_temperature. b[1] status_word_cml a communication, memory or logic fault has occurred. see status_cml. b[0] status_word_high_byte a fault/warning not listed in b[7:1] has occurred. status_vout the status_vout command returns the summary of the output voltage faults or warnings which have occurred, as shown in the following table: status_vout data contents bit(s) symbol operation b[7] status_vout_ov_fault overvoltage fault. b[6] status_vout_ov_warn overvoltage warning. b[5] status_vout_uv_warn undervoltage warning b[4] status_vout_uv_fault undervoltage fault. b[3] status_vout_max_fault vout_max fault. an attempt has been made to set the output voltage to a value higher than allowed by the vout_max command. b[2] status_vout_ton_max_fault ton_max_fault sequencing fault. b[1] status_vout_toff_max_warn not supported. always returns 0. b[0] status_vout_tracking_error not supported. always returns 0. pmbus command description
ltc2978 39 2978fc status_input the status_input command returns the summary of the v in faults or warnings which have occurred, as shown in the following table: status_input data contents bit(s) symbol operation b[7] status_input_ov_fault v in overvoltage fault b[6] status_input_ov_warn v in overvoltage warning b[5] status_input_uv_warn v in undervoltage warning b[4] status_input_uv_fault v in undervoltage fault b[3] status_input_off unit is off for insuffcient input voltage. b[2] i in overcurrent fault not supported. always returns 0. b[1] i in overcurrent warn not supported. always returns 0. b[0] pin overpower warn not supported. always returns 0. status_temperature the status_temperature command returns the summary of the temperature faults or warnings which have oc - curred, as shown in the following table: status_temperature data contents bit(s) symbol operation b[7] status_temperature_ot_fault overtemperature fault. b[6] status_temperature_ot_warn overtemperature warning. b[5] status_temperature_ut_warn undertemperature warning. b[4] status_temperature_ut_fault undertemperature fault. b[3] reserved reserved. always returns 0. b[2] reserved reserved. always returns 0. b[1] reserved reserved. always returns 0. b[0] reserved reserved. always returns 0. pmbus command description
ltc2978 40 2978fc status_cml the status_cml command returns the summary of the communication, memory and logic faults or warnings which have occurred, as shown in the following table: status_cml data contents bit(s) symbol operation b[7] status_cml_cmd_fault illegal or unsupported command fault has occurred. b[6] status_cml_data_fault illegal or unsupported data received. b[5] status_cml_pec_fault a pec fault has occurred. note: pec checking is always active in the ltc2978. any extra byte received before a stop will set status_cml_pec_fault unless the extra byte is a matching pec byte. b[4] status_cml_memory_fault a fault has occurred in the nvm. (eeprom). b[3] status_cml_processor_fault not supported, always returns 0. b[2] reserved reserved, always returns 0. b[1] status_cml_pmbus_fault a communication fault other than ones listed in this table has occurred. this is a catch all category for illegally formed i 2 c/smbus commands (example: an address byte with read =1 received immediately after a start). b[0] status_cml_unknown_fault not supported, always returns 0. status_mfr_specific the status_mfr_specific command returns manufacturer specifc status fags. bits marked fault = no are intended to support polled handshaking; these are not latched nor do they assert alertb. bits marked fault = yes assert alertb low and are cleared by clear_faults. bits marked channel = all can be read from any page. status_mfr_specific data contents bit(s) symbol operation channel fault b[7] status_mfr_discharge a v out discharge fault occurred while attempting to enter the on state current page yes b[6] status_mfr_fault1_in this channel attempted to turn on while the faultbz1 pin was asserted low, or this channel has shut down at least once in response to a faultbz1 pin asserting low since the last controln pin toggle, operation command on/off cycle or clear_faults command. current page yes b[5] status_mfr_fault0_in this channel attempted to turn on while the faultbz0 pin was asserted low, or this channel has shut down at least once in response to a faultbz0 pin asserting low since the last controln pin toggle, operation command on/off cycle or clear_faults command. current page yes b[4] status_mfr_servo_target_reached servo target has been reached. current page no b[3] status_mfr_dac_connected dac is connected and driving v dacp pin. current page no b[2] status_mfr_dac_saturated a previous servo operation terminated with maximum or minimum dac value. current page yes b[1] status_mfr_vinen_faulted_off v in_en has been deasserted due to a v out fault. all no b[0] status_mfr_watchdog_fault a watchdog fault has occurred. all yes pmbus command description
ltc2978 41 2978fc adc monitoring commands read_vin this command returns the most recent adc measured value of the voltage measured at the v in_sns pin. read_vin data contents bit(s) symbol operation b[15:0] read_vin[15:0] the data uses the l11 format. units: v read_vout this command returns the most recent adc measured value of the channels output voltage. when odd channels are confgured to measure current, the data contents use the l11 format with units in mv. read_vout data contents bit(s) symbol operation b[15:0] read_vout[15:0] the data uses the l16 format. units: v read_vout data contentsfor odd channels confgured to measure current bit(s) symbol operation b[15:0] read_vout[15:0] the data uses the l11 format. units: mv read_temperature_1 this command returns the most recent adc measured value of junction temperature in c as determined by the ltc2978s internal temperature sensor. read_temperature_1 data contents bit(s) symbol operation b[15:0] read_temperature_1 [15:0] the data uses the l11 format. units: c. pmbus_revision the pmbus_revision command register is read only and reports the ltc2978 compliance to the pmbus standard revision 1.1. pmbus_revision data contents bit(s) symbol operation b[7:0] pmbus_rev reports the pmbus standard revision compliance. this is hard-coded to 0x11 for revision 1.1. pmbus command description
ltc2978 42 2978fc manufacturer specific commands mfr_config_ltc2978 this command is used to confgure various manufacturer specifc operating parameters for each channel. mfr_config_ltc2978 data contents bit(s) symbol operation b[15:12] reserved dont care. always returns 0. b[11] mfr_confg_fast_servo_off disables fast servo when margining or trimming output voltages: 0: fast-servo enabled. 1: fast-servo disabled. b[10] mfr_confg_supervisor_resolution selects supervisor resolution: 0: high resolution C 4mv/lsb, range for v vsensepn C v vsensemn is 0v to 3.8v. 1: low resolution C 8mv/lsb, range for v vsensepn C v vsensemn is 0v to 6.0v. b[9] mfr_confg_adc_hires selects adc resolution for odd channels. this is typically used to measure current. ignored for even channels (they always use low resolution). 0: low resolution C 122v/lsb. 1: high resolution C 15.6v/lsb. b[8] mfr_confg_controln_sel selects the active control pin input (control0 or control1) for this channel. 0: select control0 pin. 1: select control1 pin. b[7] mfr_confg_servo_continuous select whether the unit should continuously servo v out after it has reached a new margin or nominal target. only applies when mfr_confg_dac_mode = 00b. 0: do not continuously servo v out after reaching initial target. 1: continuously servo v out to target. b[6] mfr_confg_servo_on_warn control re -servo on warning feature. only applies when mfr_confg_dac_mode = 00b and mfr_confg_servo_continuous = 0. 0: do not allow the unit to re-servo when a v out warning threshold is met or exceeded. 1: allow the unit to re-servo v out to nominal target if v out v(vout_ov_warn_limit) or v out v(vout_uv_warn_limit). b[5:4] mfr_confg_dac_mode determines how dac is used when channel enters on state or is already in on state. 00: soft connect (if needed) and servo to target. wait for ton_rise if just entering on state. 01: dac not connected. 10: dac connected using value from mfr_dac command. 11: dac is soft connected. after soft connect is complete mfr_dac may be written. b[3] mfr_confg_vo_en_wpu_en v out_en pin charge pumped, current-limited pull-up enable. 0: disable weak pull-up. v out_en pin driver is three-stated when channel is on. 1: use weak current-limited pull-up on v out_en pin when the channel is on. for channels 4-7 this bit is treated as a 0 regardless of its value. b[2] mfr_confg_vo_en_wpd_en v out_en pin current-limited pull-down enable. 0: use a fast n-channel device to pull down v out_en pin when the channel is off for any reason. 1: use weak current-limited pull-down to discharge v out_en pin when channel is off due to soft stop by the controln pin and/or operation command. if the channel is off due to a fault, use the fast pull-down on v out_en pin. for channels 4-7 this bit is treated as a 0 regardless of its value. b[1] mfr_confg_dac_gain dac buffer gain. 0: select dac buffer gain dac_gain_0 (1.38v full-scale) 1: select dac buffer gain dac_gain_1 (2.65v full-scale) b[0] mfr_confg_dac_pol dac output polarity. 0: encodes negative (inverting) dc/dc converter trim input. 1: encodes positive (noninverting) dc/dc converter trim input. pmbus command description
ltc2978 43 2978fc mfr_config_all_ltc2978 this command is used to confgure parameters that are common to all channels on the ic. they may be set or reviewed from any page setting. mfr_config_all_ltc2978 data contents bit(s) symbol operation b[7] mfr_confg_fault_log_enable enable fault logging to nvm in response to fault. 0: fault logging to nvm is disabled 1: fault logging to nvm is enabled b[6] mfr_vin_on_clr_faults_en vin_on rising edge to clear all latched faults 0: vin_on clear faults feature is disabled 1: vin_on clear faults feature is enabled b[5] mfr_confg_control1_pol selects active polarity of control1 pin. 0: active low (pull pin low to start unit) 1: active high (pull pin high to start unit) b[4] mfr_confg_control0_pol selects active polarity of control0 pin. 0: active low (pull pin low to start unit) 1: active high (pull pin high to start unit) b[3] mfr_confg_vin_share_enable allow this unit to hold share-clock pin low when vin_on has fallen below vin_off. when enabled, this unit will also turn all channels off in response to share-clock being held low. 0: share-clock inhibit is disabled 1: share-clock inhibit is enabled b[2] mfr_confg_all_pec_en pmbus packet error checking enable. 0: pec is accepted but not required 1: pec is required b[1] mfr_confg_all_longer_pmbus_ timeout increase pmbus timeout internal by a factor of 8. recommended for fault logging. 0: pmbus timeout is not multiplied by a factor of 8 1: pmbus timeout is multiplied by a factor of 8 b[0] mfr_confg_all_vinen_wpu_dis v in_en charge pumped, current-limited pull-up disable. 0: use weak current-limited pull-up on v in_en after power-up, as long as no faults have forced v in_en off. 1: disable weak pull-up. v in_en driver is three-stated after power-up as long as no faults have forced v in_en off. pmbus command description
ltc2978 44 2978fc mfr_faultz0_propagate, mfr_faultz1_propagate these manufacturer specifc commands enable channels that have faulted off to propagate that state to the appropri - ate fault pin. faulted off states for pages 0 through 3 can only be propagated to pins faultb00 and faultb01; this is referred to as zone 0. faulted off states for pages 4 through 7 can only be propagated to pins faultb10 and faultb11; this is referred to as zone 1. the z designator in the command name is used to indicate that this command affects different zones depending on the page. see figure 19. note that pulling a fault pin low will have no affect for channels that have mrf_faultbzn_response set to 0. the channel continues operation without interruption. this fault response is called no action in ltpowerplay?. mfr_faultz0_propagate data content bit(s) symbol operation b[7:1] reserved dont care. always returns 0. b[0] mfr_faultbz0_propagate enable fault propagation. for pages 0 through 3, zone 0 0: channels faulted off state does not assert faul tb00 low. 1: channels faulted off state asserts faul tb00 low. for pages 4 through 7, zone 1 0: channels faulted off state does not assert faul tb10 low. 1: channels faulted off state asserts faul tb10 low. mfr_faultz1_propagate data content bit(s) symbol operation b[7:1] reserved dont care. always returns 0. b[0] mfr_faultbz1_propagate enable fault propagation. for pages 0 through 3, zone 0 0: channels faulted off state does not assert faul tb01 low. 1: channels faulted off state asserts faul tb01 low. for pages 4 through 7, zone 1 0: channels faulted off state does not assert faul tb11 low. 1: channels faulted off state asserts faul tb11 low. pmbus command description
ltc2978 45 2978fc mfr_pwrgd_en this command register controls the mapping of the watchdog and channel power good status to the pwrgd pin. note that odd numbered channels whose adc is in high res mode do not contribute to power good. mfr_pwrgd_en data contents bit(s) symbol operation b[15:9] reserved read only, always returns 0s. b[8] mfr_pwrgd_en_wdog watchdog 1 = watchdog timer not-expired status is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = watchdog timer does not affect the pwrgd pin. b[7] mfr_pwrgd_en_chan7 channel 7 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. b[6] mfr_pwrgd_en_chan6 channel 6 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. b[5] mfr_pwrgd_en_chan5 channel 5 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. b[4] mfr_pwrgd_en_chan4 channel 4 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. b[3] mfr_pwrgd_en_chan3 channel 3 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. b[2] mfr_pwrgd_en_chan2 channel 2 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. b[1] mfr_pwrgd_en_chan1 channel 1 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. b[0] mfr_pwrgd_en_chan0 channel 0 1 = pwrgd status for this channel is anded with pwrgd status for any similarly enabled channels to determine when the pwrgd pin gets asserted. 0 = prwgd status for this channel does not affect the pwrgd pin. pmbus command description
ltc2978 46 2978fc mfr_faultb00_response, mfr_faultb01_response, mfr_faultb10_response and mfr_ fa u ltb11_ r es po n s e these manufacturer specifc commands share the same format and specify the response to assertions of the faultb pins. for fault zone 0, mfr_faultb00_response determines whether channels 0 to 3 shut off when the faultb00 pin is asserted, and mfr_faultb01_response determines whether channels 0 to 3 shut off when the faultb01 pin is asserted. for fault zone 1, mfr_faultb10_response determines whether channels 4 to 7 shut off when the faultb10 pin is asserted, and mfr_faultb11_response determines whether channels 4 to 7 shut off when the faultb11 pin is asserted. when a channel shuts off in response to a faultb pin, the alertb pin is asserted low and the appropriate bit is set in the status_mfr_specific register. for a graphical explanation, see the switches on the left hand side of figure 19, channel fault management block diagram. data contentsfault zone 0 response commands bit(s) symbol operation b[7:4] reserved read only, always returns 0s. b[3] mfr_faultb00_response_chan3, mfr_faultb01_response_chan3 channel 3 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. b[2] mfr_faultb00_response_chan2, mfr_faultb01_response_chan2 channel 2 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. b[1] mfr_faultb00_response_chan1, mfr_faultb01_response_chan1 channel 1 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. b[0] mfr_faultb00_response_chan0, mfr_faultb01_response_chan0 channel 0 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. data contentsfault zone 1 response commands bit(s) symbol operation b[7:4] reserved read only, always returns 0s. b[3] mfr_faultb10_response_chan7, mfr_faultb11_response_chan7 channel 7 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. b[2] mfr_faultb10_response_chan6, mfr_faultb11_response_chan6 channel 6 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. b[1] mfr_faultb10_response_chan5, mfr_faultb11_response_chan5 channel 5 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. b[0] mfr_faultb10_response_chan4, mfr_faultb11_response_chan4 channel 4 response. 0: the channel continues operation without interruption. 1: the channel shuts down if the corresponding faultbz n pin is still asserted after 10s. when the faultbzn pin subsequently deasserts, the channel turns back on, honoring ton_delay and ton_rise settings. pmbus command description
ltc2978 47 2978fc mfr_vinen_ov_fault_response this command register determines whether v out over voltage faults from a given channel cause the v in_en pin to be forced off. mfr_vinen_ov_fault_response data contents bit(s) symbol operation b[7] mfr_vinen_ov_fault_response_chan7 response to channel 7 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[6] mfr_vinen_ov_fault_response_chan6 response to channel 6 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[5] mfr_vinen_ov_fault_response_chan5 response to channel 5 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[4] mfr_vinen_ov_fault_response_chan4 response to channel 4 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[3] mfr_vinen_ov_fault_response_chan3 response to channel 3 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[2] mfr_vinen_ov_fault_response_chan2 response to channel 2 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[1] mfr_vinen_ov_fault_response_chan1 response to channel 1 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[0] mfr_vinen_ov_fault_response_chan0 response to channel 0 vout_ov_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. pmbus command description
ltc2978 48 2978fc mfr_vinen_uv_fault_response this command register determines whether v out undervoltage faults from a given channel cause the v in_en pin to be forced off. mfr_vinen_uv_fault_response data contents bit(s) symbol operation b[7] mfr_vinen_uv_fault_response_chan7 response to channel 7 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[6] mfr_vinen_uv_fault_response_chan6 response to channel 6 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[5] mfr_vinen_uv_fault_response_chan5 response to channel 5 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[4] mfr_vinen_uv_fault_response_chan4 response to channel 4 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[3] mfr_vinen_uv_fault_response_chan3 response to channel 3 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[2] mfr_vinen_uv_fault_response_chan2 response to channel 2 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[1] mfr_vinen_uv_fault_response_chan1 response to channel 1 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. b[0] mfr_vinen_uv_fault_response_chan0 response to channel 0 vout_uv_fault. 1 = disable v in_en via fast pull-down. 0 = leave v in_en as-is. mfr_retry_delay this command determines the retry interval when the ltc2978 is in retry mode in response to a fault condition. mfr_retry_delay data contents bit(s) symbol operation b[15:0] mfr_retry_delay the data uses the l11 format. this delay is counted using share_clk only. delays are rounded to the nearest 200s. units: ms. max delay is 13.1 sec. pmbus command description
ltc2978 49 2978fc mfr_restart_delay this command sets the minimum off time of a control initiated restart. if the control pin is toggled off for at least 10s then on, all dependent channels are disabled, held off for a time = mfr_restart_delay, then sequenced back on. control n pin transitions whose off time exceeds mfr_restart_delay are not affected by this command. a value of all zeros disables this feature. mfr_restart_delay data contents bit(s) symbol operation b[15:0] mfr_restart_delay the data uses the l11 format. this delay is counted using share_clk only. delays are rounded to the nearest 200s. units: ms. max delay is 13.1 sec. mfr_vout_peak this command returns the maximum adc measured value of the channels output voltage. this command is not sup - ported for odd channels that are confgured to measure current. this register is reset to 0xf800 (0.0) when the ltc2978 emerges from power-on reset or when a clear_faults command is executed. mfr_vout_peak data contents bit(s) symbol operation b[15:0] mfr_vout_peak[15:0] the data uses the l16 format. units: v. mfr_vin_peak this command returns the maximum adc measured value of the input voltage. this register is reset to 0x7c00 (C2 25 ) when the ltc2978 emerges from power-on reset or when a clear_faults command is executed. mfr_vin_peak data contents bit(s) symbol operation b[15:0] mfr_vin_peak[15:0] the data uses the l11 format. units: v mfr_temperature_peak this command returns the maximum adc measured value of junction temperature in c as determined by the ltc2978s internal temperature sensor. this register is reset to 0x7c00 (C2 25 ) when the ltc2978 emerges from power-on reset or when a clear_faults command is executed. mfr_temperature_peak data contents bit(s) symbol operation b[15:0] mfr_temperature_peak[15:0] the data uses the l11 format. units: c. pmbus command description
ltc2978 50 2978fc mfr_dac this command register allows the user to directly program the 10-bit dac. manual dac writes require the channel to be in the on state,ton_rise to have expired and mfr_config_ltc2978 b[5:4] = 10b or 11b. writing mfr_config_ ltc2978 b[5:4] = 10b commands the dac to hard connect with the value in mfr_dac_direct_val. writing b[5:4] = 11b commands the dac to soft connect. once the dac has soft connected, mfr_dac_direct_val returns the value that al - lowed the dac to be connected without perturbing the power supply. mfr_dac data contents bit(s) symbol operation b[15:10] reserved read only, always returns 0. b[9:0] mfr_dac_direct_val dac code value. mfr_powergood_assertion_delay this command register allows the user to program the delay from when the internal power good signal becomes valid until the power good output is asserted. this delay is counted using share_clk if available, otherwise the internal oscillator is used. this delay is internally limited to 13.1 seconds, and rounded to the nearest 200s. the read value of this command always returns what was last written and does not refect internal limiting. mfr_powergood_assertion_delay data contents bit(s) symbol operation b[15:0] mfr_powergood_assertion_delay the data uses the l11 format. this delay is counted using share_clk if available, otherwise the internal oscillator is used. delays are rounded to the nearest 200s. units: ms. max delay is 13.1 sec. watchdog operation a non zero write to the mfr_watchdog_t register will reset the watchdog timer. low-to-high transitions on the wdi/ resetb pin also reset the watchdog timer. if the timer expires, alertb is asserted and the pwrgd output is optionally deasserted and then reasserted after mfr_pwrgd_assertion_delay ms. writing 0 to either the mfr_watch_dog_t or mfr_watchdog_t_first registers will disable the timer. mfr_watchdog_t_first and mfr_watchdog_t the mfr_watchdog_t_first register allows the user to program the duration of the frst watchdog timer interval following assertion of the power good signal, assuming the power good signal refects the status of the watchdog timer. if assertion of power good is not conditioned by the watchdog timers status, then mfr_watchdog_t_first applies to the frst timing interval after the timer is enabled. writing a value of 0ms to the mfr_watchdog_t_first register disables the watchdog timer. the mfr_watchdog_t register allows the user to program watchdog time intervals subsequent to the mfr_ watchdog_t_first timing interval. writing a value of 0ms to the mfr_watchdog_t register disables the watchdog timer. a non-zero write to mfr_watchdog_t will reset the watchdog timer. pmbus command description
ltc2978 51 2978fc mfr_watchdog_t_por and mfr_watchdog_t data contents bit(s) symbol operation b[15:0] mfr_watchdog_t_frst mfr_watchdog_t the data uses the l11 format. these timers operate on an internal clock. the mfr_watchdog_t timer will align to share_clk if it is running. delays are rounded to the nearest 10s for _t and 1ms for _t_frst. writing a zero value for y to the mfr_watchdog_t or mfr_watchdog_t_frst registers will disable the watchdog timer. units: ms. max timeout is 0.6 sec for _t and 65 sec for _t_frst mfr_page_ff_mask the mfr_page_ff_mask command is used to select which channels respond when the global page command (page=0xff) is in use. mfr_page_ff_mask data contents bit(s) symbol operation b[7] mfr_page_ff_mask_chan7 channel 7 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[6] mfr_page_ff_mask_chan6 channel 6 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[5] mfr_page_ff_mask_chan5 channel 5 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[4] mfr_page_ff_mask_chan4 channel 4 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[3] mfr_page_ff_mask_chan3 channel 3 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[2] mfr_page_ff_mask_chan2 channel 2 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[1] mfr_page_ff_mask_chan1 channel 1 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses b[0] mfr_page_ff_mask_chan0 channel 0 masking of global page command (page=0xff) accesses 0 = ignore global page command accesses 1 = fully respond to global page command accesses pmbus command description
ltc2978 52 2978fc mfr_pads the mfr_pads command provides read only access to slow frequency digital pads. the input values presented in bits[9:0] are before any deglitching logic. mfr_pads_pwrgd_drive data contents bit(s) symbol operation b[15] mfr_pads_pwrgd_drive 0 = pwrgd pad is being driven low by this chip 1 = pwrgd pad is not being driven low by this chip b[14] mfr_pads_alertb_drive 0 = alertb pad is being driven low by this chip 1 = alertb pad is not being driven low by this chip b[13:10] mfr_pads_faultb_drive[3.0] bit[3] used for faultb00 pad, bit[2] used for faultb01 pad, bit[1] used for faultb10 pad, bit[0] used for faultb11 pad as follows: 0 = faultbzn pad is being driven low by this chip 1 = faultbzn pad is not being driven low by this chip b[9:8] mfr_pads_asel1[1:0] 11: logic high detected on asel1 input pad 10: asel1 input pad is foating 01: reserved 00: logic low detected on asel1 input pad b[7:6] mfr_pads_asel0[1:0] 11: logic high detected on asel0 input pad 10: asel0 input pad is foating 01: reserved 00: logic low detected on asel0 input pad b[5] mfr_pads_control1 1: logic high detected on control1 pad 0: logic low detected on control1 pad b[4] mfr_pads_control0 1: logic high detected on control0 pad 0: logic low detected on control0 pad b[3:0] mfr_pads_faultb[3:0] bit[3] used for faultb00 pad, bit[2] used for faultb01 pad, bit[1] used for faultb10 pad, bit[0] used for faultb11 pad as follows: 1: logic high detected on faultbz n pad 0: logic low detected on faultbz n pad mfr_i2c_base_address the mfr_i2c_base_address command determines the base value for the i 2 c/smbus address byte. offsets of 0 to 9 are added to this base address to make the device i 2 c/smbus address. the part responds to the device address. mfr_i2c_base_address data contents bit(s) symbol operation b[7] reserved read only, always returns 0. b[6:0] i2c_base_address this 7-bit value determines the base value of the 7-bit i 2 c/smbus address. see operation section: device address. mfr_special_id this register contains the manufacturer id for the ltc2978. mfr_special_id data contents bit(s) symbol operation b[15:0] mfr_special_id read only, always returns 0x0121 pmbus command description
ltc2978 53 2978fc mfr_special_lot these paged registers contain information that identifes the user confguration that was programmed at the factory. mfr_special_lot data contents bit(s) symbol operation b[7:0] mfr_special_lot contains the ltc default special lot number. contact the factory to request a custom factory programmed user confgura - tion and special lot number. mfr_vout_discharge_threshold this register contains the coeffcient that multiplies vout_command in order to determine the off thresh - old voltage for the associated output. if the output voltage has not decayed below mfr_vout_discharge_ threshold ? vout_command prior to the channel being commanded to enter/re-enter the on state, bit [7] in the status_mfr_specific register will be set and the alertb pin will be asserted low. in addition, the channel will not enter the on state until the output has decayed below its off threshold voltage. other channels can be held off if a particular output has failed to discharge by using the bidirectional faultbz n pins (refer to the mfr_faultbz n _response and mfr_faultbzn _propagate registers). mfr_vout_discharge_threshold data contents bit(s) symbol operation b[15:0] mfr_vout_discharge_ threshold the data uses the l11 format. units: dimensionless, this register contains a coeffcient. mfr_common this command returns status information for the share-clock pin (share_clk) and the write-protect pin (wp). mfr_common data contents bit(s) symbol operation b[7:2] reserved read only, always returns 0s b[1] mfr_common_ share_clk returns status of share-clock pin 1: share-clock pin is being held low 0: share-clock pin is active b[0] mfr_common_ write_protect returns status of write-protect pin 1: write-protect pin is high 0: write-protect pin is low mfr_spare0 this 16-bit wide register can be used to store miscellaneous information. the contents of this register may be stored and recalled from eeprom using the store_user_all and restore_user_all commands, respectively. mfr_spare2 these 16-bit wide, paged registers can be used to store miscellaneous information. the contents of these registers may be stored and recalled from eeprom using the store_user_all and restore_user_all commands, respectively. pmbus command description
ltc2978 54 2978fc mfr_vout_min this command returns the minimum adc measured value of the channels output voltage. this register is reset to 0xffff (7.999) when the ltc2978 emerges from power-on reset or when a clear_faults command is executed. when odd channels are confgured to measure current, this command is not supported. updates are disabled when undervoltage detection is disabled. mfr_vout_min data contents bit(s) symbol operation b[15:0] mfr_vout_min the data uses the l16 format. units: v. mfr_vin_min this command returns the minimum adc measured value of the input voltage. this register is reset to 0x7bff (approximately 2 25 ) when the ltc2978 emerges from power-on reset or when a clear_faults command is executed. updates are disabled when unit is off for insuffcient input voltage. mfr_vin_min data contents bit(s) symbol operation b[15:0] mfr_vin_min the data uses the l11 format. units: v. mfr_temperature_min this command returns the minimum adc measured value of junction temperature in c as determined by the ltc2978s internal temperature sensor. this register is reset to 0x7bff (approximately 2 25 ) when the ltc2978 emerges from power-on reset or when a clear_faults command is executed. mfr_temperature_min data contents bit(s) symbol operation b[15:0] mfr_temperature_min the data uses the l11 format. units: c. fault log operation a conceptual diagram of the fault log is shown in figure 13. the fault log provides black box capability to the ltc2978. during normal operation, the contents of the status registers, the output voltage/current readings, temperature readings as well as peak and min values of these quantities are stored in a continuously updated buffer in ram. you can think of the operation as being similar to a strip chart recorder. when a fault occurs, the contents are written into eeprom for nonvolatile storage. the eeprom fault log is then locked. the part can be powered down with the fault log being available for reading at a later time. pmbus command description
ltc2978 55 2978fc figure 13. fault log conceptual diagram 2978 f13 adc readings continuously fill buffer time of fault transfer to eeprom and lock after fault read from eeprom and lock buffer ram 255 bytes eeprom 255 bytes 8 . . . . . . mfr_fault_log_store this command allows the user to transfer data from the ram buffer to eeprom. mfr_fault_log_restore this command allows the user to transfer a copy of the fault-log data from the eeprom to the ram buffer. after a restore the ram buffer is locked until a successful mfr_fault_log read. mfr_fault_log_clear this command initializes the eeprom block reserved for fault logging. any previous fault log stored in eeprom will be erased by this operation. mfr_fault_log_status read only. this register is used to manage fault log events. mfr_fault_log_status_eeprom is set after a mfr_fault_log_store command or a faulted-off event triggers a transfer of the fault log from ram to eeprom. this bit is cleared by a mfr_fault_log_clear command. mfr_fault_log_status_ram is set after a mfr_fault_log_restore to indicate that the data in the ram has been restored from eeprom and not yet read using a mfr_fault_log command. this bit is cleared only by a successful execution of an mfr_fault_log command. mfr_fault_log_status data contents bit(s) symbol operation b[1] mfr_fault_log_status_ram fault log ram status: 0: the fault log ram allows updates. 1: the fault log ram is locked until the next mfr_fault_log read. b[0] mfr_fault_log_status_eeprom fault log eeprom status: 0: the transfer of the fault log ram to the eeprom is enabled. 1: the transfer of the fault log ram to the eeprom is inhibited. pmbus command description
ltc2978 56 2978fc mfr_fault_log read only. this 2040-bit data block contains a copy of the ram buffer fault log. the ram buffer is continuously updated after each adc conversion as long as mfr_fault_ log_status_ram is clear. with mfr_confg_fault_log_en = 1 and mfr_fault_log_status_eeprom = 0, the ram buffer is transferred to eeprom whenever an ltc2978 fault causes a channel to latch off or a mfr_fault_log_store com - mand is received. mfr_fault_log_status_eeprom is set high after the ram buffer is transferred to eeprom and not cleared until a mfr_fault_log_clear is received, even if the ltc2978 is reset or powered down. fault log eeprom transfers are not initiated as a result of status_mfr_dis - charge, status_mfr_fault1_in or status_mfr_fault0_in events. during a mfr_fault_log read, data is returned as defned by the following table. the fault log data is parti - tioned into two sections. the frst section is referred to as the preamble and contains the position-last pointer, time information and peak and minimum values. the second section contains a chronological record of telemetry and requires position-last for proper interpretation. the fault log stores approximately 1 to 2 seconds of telemetry. to prevent timeouts during block reads, it is recommended that mfr_config_all_ltc2978 b[1] be set to 1. table 2. data block contents d ata byte* description position_last[7:0] 0 position of fault log pointer when fault occurred. sharedtime[7:0] 1 41-bit share-clock counter value when fault occurred. counter lsb is in 200s increments. this counter is cleared at power-up or after the ltc2978 is reset sharedtime[15:8] 2 sharedtime[23:16] 3 sharedtime[31:24] 4 sharedtime[39:32] 5 sharedtime[40] 6 mfr_vout_peak0[7:0] 7 mfr_vout_peak0[15:8] 8 mfr_vout_min0[7:0] 9 mfr_vout_min0[15:8] 10 mfr_vout_peak1[7:0] 11 mfr_vout_peak1[15:8] 12 mfr_vout_min1[7:0] 13 mfr_vout_min1[15:8] 14 mfr_vin_peak[7:0] 15 mfr_vin_peak[15:8] 16 mfr_vin_min[7:0] 17 mfr_vin_min[15:8] 18 mfr_vout_peak2[7:0] 19 mfr_vout_peak2[15:8] 20 mfr_vout_min2[7:0] 21 mfr_vout_min2[15:8] 22 mfr_vout_peak3[7:0] 23 mfr_vout_peak3[15:8] 24 mfr_vout_min3[7:0] 25 mfr_vout_min3[15:8] 26 mfr_temp_peak[7:0] 27 mfr_temp_peak[15:8] 28 mfr_ temp_min[7:0] 29 mfr_ temp_min[15:8] 30 mfr_vout_peak4[7:0] 31 mfr_vout_peak4[15:8] 32 mfr_vout_min4[7:0] 33 mfr_vout_min4[15:8] 34 mfr_vout_peak5[7:0] 35 mfr_vout_peak5[15:8] 36 mfr_vout_min5[7:0] 37 mfr_vout_min5[15:8] 38 mfr_vout_peak6[7:0] 39 mfr_vout_peak6[15:8] 40 mfr_vout_min6[7:0] 41 mfr_vout_min6[15:8] 42 pmbus command description
ltc2978 57 2978fc table 2. data block contents d ata byte* description mfr_vout_peak7[7:0] 43 mfr_vout_peak7[15:8] 44 mfr_vout_min7[7:0] 45 mfr_vout_min7[15:8] 46 47 bytes for preamble fault_log [position_last] 47 fault_log 48 . . . fault_log 237 last valid byte reserved 238-254 number of loops (238-47)/40 = 4.8 *note: pmbus data byte numbers start at 1 rather than 0. position_last is the frst byte returned after byte count = oxff. see block read protocol. the data returned between bytes 47 and 237 of the previous table is interpreted using position_last and the following table. the key to identifying byte 47 is to locate the data corresponding to position = position_last in the next table. subsequent bytes are identifed by decrementing the value of position. for example: if position_last = 9 then the frst data returned in byte position 47 of a block read is read_vin[15:8] followed by read_vin[7:0] followed by status_mfr of page 1. see table 3. table 3. interpreting cyclical loop position d ata 0 read_vout0[7:0] 1 read_vout0[15:8] 2 status_vout0 3 status_mfr0 4 read_vout1[7:0] 5 read_vout1[15:8] 6 status_vout1 7 status_mfr1 8 read_vin[7:0] 9 read_vin[15:8] 10 status_vin 11 reserved 12 read_vout2[7:0] 13 read_vout2[15:8] 14 status_vout2 15 status_mfr2 16 read_vout3[7:0] table 3. interpreting cyclical loop position d ata 17 read_vout3[15:8] 18 status_vout3 19 status_mfr3 20 read_temperature_1[7:0] 21 read_temperature_1[15:8] 22 status_temp 23 reserved 24 read_vout4[7:0] 25 read_vout4[15:8] 26 status_vout4 27 status_mfr4 28 read_vout5[7:0] 29 read_vout5[15:8] 30 status_vout5 31 status_mfr5 32 read_vout6[7:0] 33 read_vout6[15:8] 34 status_vout6 35 status_mfr6 36 read_vout7[7:0] 37 read_vout7[15:8] 38 status_vout7 39 status_mfr7 total bytes =40 the following table fully decodes a sample fault log read to help clarify the cyclical nature of the operation. mfr_fault_log data block contents preamble information byte number decimal byte number hex d ata description 0 00 position_last[7:0] = 9 position of fault-log pointer when fault occured. 1 01 sharedtime[7:0] 41-bit share- clock counter value when fault occurred. counter lsb is in 200s increments. 2 02 sharedtime[15:8] 3 03 sharedtime[23:16] 4 04 sharedtime[31:24] pmbus command description
ltc2978 58 2978fc byte number decimal byte number hex d ata description 5 05 sharedtime[39:32] 6 06 sharedtime[40] 7 07 mfr_vout_peak0[7:0] 8 08 mfr_vout_peak0[15:8] 9 09 mfr_vout_min0[7:0] 10 0a mfr_vout_min0[15:8] 11 0b mfr_vout_peak1[7:0] 12 0c mfr_vout_peak1[15:8] 13 0d mfr_vout_min1[7:0] 14 0e mfr_vout_min1[15:8] 15 0f mfr_vin_peak[7:0] 16 10 mfr_vin_peak[15:8] 17 11 mfr_vin_min[7:0] 18 12 mfr_vin_min[15:8] 19 13 mfr_vout_peak2[7:0] 20 14 mfr_vout_peak2[15:8] 21 15 mfr_vout_min2[7:0] 22 16 mfr_vout_min2[15:8] 23 17 mfr_vout_peak3[7:0] 24 18 mfr_vout_peak3[15:8] 25 19 mfr_vout_min3[7:0] 26 1a mfr_vout_min3[15:8] 27 1b mfr_temp_peak[7:0] 28 1c mfr_temp_peak[15:8] 29 1d mfr_ temp_min[7:0] 30 1e mfr_ temp_min[15:8] 31 1f mfr_vout_peak4[7:0] 32 20 mfr_vout_peak4[15:8] 33 21 mfr_vout_min4[7:0] 34 22 mfr_vout_min4[15:8] 35 23 mfr_vout_peak5[7:0] 36 24 mfr_vout_peak5[15:8] 37 25 mfr_vout_min5[7:0] 38 26 mfr_vout_min5[15:8] 39 27 mfr_vout_peak6[7:0] 40 28 mfr_vout_peak6[15:8] 41 29 mfr_vout_min6[7:0] 42 2a mfr_vout_min6[15:8] 43 2b mfr_vout_peak7[7:0] byte number decimal byte number hex d ata description 44 2c mfr_vout_peak7[15:8] 45 2d mfr_vout_min7[7:0] 46 2e mfr_vout_min7[15:8] end of preamble cyclical data loops byte number decimal byte number hex loop byte number decimal data loop 0 40 bytes per loop 47 2f 9 read_vin[15:8] position_last 48 30 8 read_vin[7:0] 49 31 7 status_mfr1 50 32 6 status_vout1 51 33 5 read_vout1[15:8] 52 34 4 read_vout1[7:0] 53 35 3 status_mfr0 54 36 2 status_vout0 55 37 1 read_vout0[15:8] 56 38 0 read_vout0[7:0] byte number decimal byte number hex loop byte number decimal data loop 1 40 bytes per loop 57 39 39 status_mfr7 58 3a 38 status_vout7 59 3b 37 read_vout7[15:8] 60 3c 36 read_vout7[7:0] 61 3d 35 status_mfr6 62 3e 34 status_vout6 63 3f 33 read_vout6[15:8] 64 40 32 read_vout6[7:0] 65 41 31 status_mfr5 66 42 30 status_vout5 67 43 29 read_vout5[15:8] 68 44 28 read_vout5[7:0] 69 45 27 status_mfr4 70 46 26 status_vout4 71 47 25 read_vout4[15:8] 72 48 24 read_vout4[7:0] 73 49 23 reserved 74 4a 22 status_temp pmbus command description
ltc2978 59 2978fc byte number decimal byte number hex loop byte number decimal data loop 1 40 bytes per loop 75 4b 21 read_ temperature_1[15:8] 76 4c 20 read_ temperature_1[7:0] 77 4d 19 status_mfr3 78 4e 18 status_vout3 79 4f 17 read_vout3[15:8] 80 50 16 read_vout3[7:0] 81 51 15 status_mfr2 82 52 14 status_vout2 83 53 13 read_vout2[15:8] 84 54 12 read_vout2[7:0] 85 55 11 reserved 86 56 10 status_vin 87 57 9 read_vin[15:8] 88 58 8 read_vin[7:0] 89 59 7 status_mfr1 90 5a 6 status_vout1 91 5b 5 read_vout1[15:8] 92 5c 4 read_vout1[7:0] 93 5d 3 status_mfr0 94 5e 2 status_vout0 95 5f 1 read_vout0[15:8] 96 60 0 read_vout0[7:0] byte number decimal byte number hex loop byte number decimal data loop 2 40 bytes per loop 97 61 39 status_mfr7 98 62 38 status_vout7 99 63 37 read_vout7[15:8] 100 64 36 read_vout7[7:0] 101 65 35 status_mfr6 102 66 34 status_vout6 103 67 33 read_vout6[15:8] 104 68 32 read_vout6[7:0] 105 69 31 status_mfr5 106 6a 30 status_vout5 107 6b 29 read_vout5[15:8] 108 6c 28 read_vout5[7:0] byte number decimal byte number hex loop byte number decimal data loop 2 40 bytes per loop 109 6d 27 status_mfr4 110 6e 26 status_vout4 111 6f 25 read_vout4[15:8] 112 70 24 read_vout4[7:0] 113 71 23 reserved 114 72 22 status_temp 115 73 21 read_temperature_ 1[15:8] 116 74 20 read_temperature_ 1[7:0] 117 75 19 status_mfr3 118 76 18 status_vout3 119 77 17 read_vout3[15:8] 120 78 16 read_vout3[7:0] 121 79 15 status_mfr2 122 7a 14 status_vout2 123 7b 13 read_vout2[15:8] 124 7c 12 read_vout2[7:0] 125 7d 11 reserved 126 7e 10 status_vin 127 7f 9 read_vin[15:8] 128 80 8 read_vin[7:0] 129 81 7 status_mfr1 130 82 6 status_vout1 131 83 5 read_vout1[15:8] 132 84 4 read_vout1[7:0] 133 85 3 status_mfr0 134 86 2 status_vout0 135 87 1 read_vout0[15:8] 136 88 0 read_vout0[7:0] byte number decimal byte number hex loop byte number decimal data loop 3 40 bytes per loop 137 89 39 status_mfr7 138 8a 38 status_vout7 139 8b 37 read_vout7[15:8] 140 8c 36 read_vout7[7:0] 141 8d 35 status_mfr6 pmbus command description
ltc2978 60 2978fc pmbus command description byte number decimal byte number hex loop byte number decimal data loop 3 40 bytes per loop 142 8e 34 status_vout6 143 8f 33 read_vout6[15:8] 144 90 32 read_vout6[7:0] 145 91 31 status_mfr5 146 92 30 status_vout5 147 93 29 read_vout5[15:8] 148 94 28 read_vout5[7:0] 149 95 27 status_mfr4 150 96 26 status_vout4 151 97 25 read_vout4[15:8] 152 98 24 read_vout4[7:0] 153 99 23 reserved 154 9a 22 status_temp 155 9b 21 read_temperature_ 1[15:8] 156 9c 20 read_temperature_ 1[7:0] 157 9d 19 status_mfr3 158 9e 18 status_vout3 159 9f 17 read_vout3[15:8] 160 a0 16 read_vout3[7:0] 161 a1 15 status_mfr2 162 a2 14 status_vout2 163 a3 13 read_vout2[15:8] 164 a4 12 read_vout2[7:0] 165 a5 11 reserved 166 a6 10 status_vin 167 a7 9 read_vin[15:8] 168 a8 8 read_vin[7:0] 169 a9 7 status_mfr1 170 aa 6 status_vout1 171 ab 5 read_vout1[15:8] 172 ac 4 read_vout1[7:0] 173 ad 3 status_mfr0 174 ae 2 status_vout0 175 af 1 read_vout0[15:8] 176 b0 0 read_vout0[7:0] byte number decimal byte number hex loop byte number decimal data loop 4 40 bytes per loop 177 b1 39 status_mfr7 178 b2 38 status_vout7 179 b3 37 read_vout7[15:8] 180 b4 36 read_vout7[7:0] 181 b5 35 status_mfr6 182 b6 34 status_vout6 183 b7 33 read_vout6[15:8] 184 b8 32 read_vout6[7:0] 185 b9 31 status_mfr5 186 ba 30 status_vout5 187 bb 29 read_vout5[15:8] 188 bc 28 read_vout5[7:0] 189 bd 27 status_mfr4 190 be 26 status_vout4 191 bf 25 read_vout4[15:8] 192 c0 24 read_vout4[7:0] 193 c1 23 reserved 194 c2 22 status_temp 195 c3 21 read_temperature_ 1[15:8] 196 c4 20 read_temperature_ 1[7:0] 197 c5 19 status_mfr3 198 c6 18 status_vout3 199 c7 17 read_vout3[15:8] 200 c8 16 read_vout3[7:0] 201 c9 15 status_mfr2 202 ca 14 status_vout2 203 cb 13 read_vout2[15:8] 204 cc 12 read_vout2[7:0] 205 cd 11 reserved 206 ce 10 status_vin 207 cf 9 read_vin[15:8] 208 d0 8 read_vin[7:0] 209 d1 7 status_mfr1 210 d2 6 status_vout1 211 d3 5 read_vout1[15:8]
ltc2978 61 2978fc byte number decimal byte number hex loop byte number decimal data loop 4 40 bytes per loop 212 d4 4 read_vout1[7:0] 213 d5 3 status_mfr0 214 d6 2 status_vout0 215 d7 1 read_vout0[15:8] 216 d8 0 read_vout0[7:0] byte number decimal byte number hex loop byte number decimal data loop 5 40 bytes per loop 217 d9 39 status_mfr7 218 da 38 status_vout7 219 db 37 read_vout7[15:8] 220 dc 36 read_vout7[7:0] 221 dd 35 status_mfr6 222 de 34 status_vout6 223 df 33 read_vout6[15:8] 224 e0 32 read_vout6[7:0] 225 e1 31 status_mfr5 226 e2 30 status_vout5 227 e3 29 read_vout5[15:8] 228 e4 28 read_vout5[7:0] 229 e5 27 status_mfr4 230 e6 26 status_vout4 231 e7 25 read_vout4[15:8] 232 e8 24 read_vout4[7:0] 233 e9 23 reserved 234 ea 22 status_temp 235 eb 21 read_temperature_ 1[15:8] 236 ec 20 read_temperature_ 1[7:0] 237 ed 19 status_mfr3 last valid fault log byte reserved bytes 238 ee 0x00 bytes ee - fe return 0x00 but must be read 239 ef 0x00 240 f0 0x00 241 f1 0x00 242 f2 0x00 243 f3 0x00 244 f4 0x00 245 f5 0x00 246 f6 0x00 247 f7 0x00 248 f8 0x00 249 f9 0x00 250 fa 0x00 251 fb 0x00 252 fc 0x00 253 fd 0x00 254 fe 0x00 use one block read command to read 255 bytes total, from 0x00 to 0xfe pmbus command description
ltc2978 62 2978fc applications information overview the ltc2978 is a power management ic that is capable of sequencing, margining, trimming, supervising output voltage for ov/uv conditions, providing fault manage - ment, and voltage read back for eight dc/dc converters. input voltage and ltc2978 junction temperature read back are also available. odd numbered channels can be confgured to read back sense resistor voltages. multiple ltc2978s can be synchronized to operate in unison using the share_clk, faultb and control pins. the ltc2978 utilizes a pmbus compliant interface and command set. powering the ltc2978 the ltc2978 can be powered two ways. the frst method requires that a voltage between 4.5v and 15v be applied to the v pwr pin. see figure 14. an internal linear regula - tor converts v pwr down to 3.3v which drives all of the internal circuitry of the ltc2978. alternatively, power from an external 3.3v supply may be applied directly to the v dd33 pins 16 and 17 using a volt - age between 3.13v and 3.47v. tie v pwr to v dd33 pins. see figure 15. all functionality is available when using this alternate power method. the higher voltages needed for the v out_en[0:3] pins and bias for the v sense pins are charge pumped from v dd33 . setting command register values the command register settings described herein are for the purpose of understanding and software development in a host processor. in actual practice, the ltc2978 can be completely confgured for standalone operation with the ltc usb to i 2 c/smbus/pmbus controller and software gui using intuitive menu driven objects. sequence, servo, margin and restart operations command units on or off three control parameters determine how a particular channel is turned on and off. the control pins, the operation command and the value of the input voltage measured at the v in_sns pin (v in ). in all cases, v in must exceed vin_on in order to enable a start. when v in drops below vin_off an immediate off of all channels will result. refer to the operation section in the data sheet for a detailed description of the on_off_config command. some examples of typical on/off confgurations are: 1. a dc/dc converter may be confgured to turn on anytime v in exceeds vin_on. 2. a dc/dc converter may be confgured to turn on only when it receives an operation command. 3. a dc/dc converter may be confgured to turn on only via the control pin. 4. a dc/dc converter may be confgured to turn on only when it receives an operation command and the control pin is asserted. figure 14. powering lt2978 directly from an intermediate bus figure 15. powering ltc2978 from external 3.3v supply v pwr v dd33 v dd33 v dd25 v in_sns ltc2978 0.1f 0.1f 4.5v < v pwr < 15v gnd 0.1f *some details omitted for clarity 2978 f14 v dd33 v dd33 v dd25 v pwr ltc2978 0.1f 0.1f gnd *some details omitted for clarity 2978 f15 external 3.3v
ltc2978 63 2978fc figure 16. typical on sequence using control pin applications information on sequencing the ton_delay command sets the amount of time that a channel will wait following the start of an on sequence before its v out_en pin will enable a dc/dc converter. once the dc/dc converter has been enabled, the ton_rise command determines the amount of time the ltc2978 waits before soft connecting the v dacpn output and ser - voing the dc/dc converter output to vout_command. the ton_max_fault_limit command determines the amount of time after the dc/dc converter has been enabled that an undervoltage condition will be tolerated before a fault occurs. if a ton_max_fault occurs, the channel can be confgured to disable the dc/dc converter and propagate the fault to other channels using the bidirectional faultb pins. figure 16 shows a typical on-sequence using the control pin. on state operation once a channel has reached the on state, the operation command can be used to command the dc/dc converters output to margin high, margin low, or return to a nominal output voltage indicated by vout_command. the user also has the option of confguring a channel to continuously trim the output of the dc/dc converter to the vout_command voltage, or the channels v dacp n output can be placed in a high impedance state thus allowing the dc/dc converter output voltage to go to its nominal value, v dc n (nom) . refer to the mfr_config_ltc2978 command for details on how to confgure the output voltage servo. servo modes the adc, dac and internal processor comprise a digital servo loop that can be confgured to operate in several useful modes. the servo target refers to the desired output voltage. continuous/noncontinuous trim mode. mfr_config_ ltc2978 b[7]. in continuous trim mode, the servo will update the dac in a closed loop fashion each time it takes a v out reading. the update rate is determined by the time it takes to step through the adc mux which is typically 100ms. see electrical characteristics table note 6. in noncontinuous trim mode, the servo will drive the dac until the adc measures the output voltage desired and then stop updating the dac. noncontinuous servo on warn mode. mfr_config_ ltc2978 b[7] = 0, b[6] = 1. when in noncontinuous mode, the ltc2978 can additionally retrim (reservo) the output if the output drifts beyond the ov or uv warn limits. dac modes the dacs that drive the v dacn pins can operate in several useful modes. see mfr_config_ltc2978. ? soft connect. using the ltc patented soft connect feature, the dac output is driven to within 1 lsb of the voltage at the dc/dc's feedback node before connect - ing to avoid introducing transients on the output. this mode is used when servoing the output voltage. during start-up, the ltc2978 waits until ton_rise has expired before connecting the dac. this is the most common operating mode. ? disconnected. dac output is high z. ? dac manual with soft connect. non servo mode. the dac soft connects to the feedback node . the dac code is driven to match the voltage at the feedback node. after connection, the dac is moved by writing dac codes to the device. vout_0v_fault_limit dac soft-connects and begins adjusting output vout_uv_fault_limit v control v out_en v out ton_delay ton_rise 2978 f16 v dc(nom) v out_command ton_max_fault_limit
ltc2978 64 2978fc ? dac manual with hard connect. non servo mode. the dac hard connects to the feedback node at the value in mfr_dac. after connection, the dac is moved by writing dac codes to the device. margining the ltc2978 margins and trims the output of a dc/dc converter by driving current into or out of the feedback node or the trim pin. preset limits for margining are stored in the vout_margin_high/low registers. margining is actuated by writing the appropriate bits to the opera - tion register. margining requires the dac to be connected. margin requests that occur when the dac is disconnected will force the dac to soft connect. when in the margin high/ low state, the dac cannot be disconnected. the dac can only be disconnected from the on state. off sequencing an off sequence is initiated using the control pin or the operation command. the toff_delay command determines the amount of time that elapses from the be - ginning of the off sequence until each channels v out_en pin is pulled low thus disabling its dc/dc converter. v out off threshold voltage the mfr_vout_discharge_threshold command register allows the user to specify the off threshold that the output voltage must decay below before the channel can enter/re-enter the on state. the off threshold voltage is specifed by multiplying mfr_vout_discharge_ threshold and vout_command. in the event that an output voltage has not decayed below its off threshold before attempting to enter the on state, the channel will continue to be held off, the appropriate bit is set in the status_mfr_specific register, and the alertb pin will be asserted low. when the output voltage has decayed below its off threshold, the channel can enter the on state. automatic restart via mfr_restart_delay command and controln pin an automatic restart sequence can be initiated by driving the control pin to the off state for >10s then releas- ing it. the automatic restart disables all v out_en pins that are mapped to a particular control pin for a time period = mfr_restart_delay and then starts all dc-dc converters according to their respective ton_delays. (see figure 17). v out_enn pins are mapped to one of the control pins by the mfr_config_ltc2978 command. this feature allows a host that is about to reset to restart the power in a controlled manner after it has recovered. applications information figure 17. off sequence with automatic restart v control v out_end control pin bounce toff_delay0 ton_delay0 2978 f17 mfr_restart_delay fault management output overvoltage and undervoltage faults the high speed voltage supervisor ov and uv fault thresh - olds are confgured using the vout_ov_fault_limit and vout_uv_fault_limit commands, respectively. the vout_ov_fault_response and vout_uv_fault_re - sponse commands determine the responses to ov/ uv faults. fault responses can range from disabling the dc/dc converter immediately, waiting to see if the fault condition persists for some interval before disabling the dc/dc converter, or allowing the dc/dc converter to continue operating in spite of the fault. if a dc/dc converter is disabled, the ltc2978 can be confgured to retry or latch-off. the retry interval is specifed using the
ltc2978 65 2978fc applications information mfr_retry_delay command. latched faults are reset by toggling the control pin, using the operation com - mand, or removing and reapplying the bias voltage to the v in_sns pin. all fault and warning conditions result in the alertb pin being asserted low and the corresponding bits being set in the status registers. the clear_faults command resets the contents of the status registers and deasserts the alertb output. output overvoltage and undervoltage warnings ov and uv warning threshold voltages are processed by the ltc2978s adc. these thresholds are set by the vout_ov_warn_limit and vout_uv_warn_limit commands respectively. if a warning occurs, the corre - sponding bits are set in the status registers and the alertb output is asserted low. note that a warning will never cause a v out_en output pin to disable a dc/dc converter. confguring the v in_en output the v in_en output may be used to disable the interme- diate bus voltage in the event of an output ov or uv fault. use the mfr_vinen_ov_fault_response and mfr_vinen_uv_fault_response registers to confg - ure the v in_en pin to assert low in response to vout_ov/ uv fault conditions. the v in_en output will stop pulling low when the ltc2978 is commanded to re-enter the on state following a faulted-off condition. a charge-pumped 5a pull-up to 12v is also available on the v in_en output. refer to the mfr_config_all_ltc2978 register description in the operation section for more information. figure 18 shows an application circuit where the v in_en output is used to trigger a scr crowbar on the intermediate bus in order to protect the dc/dc converters load from a catastrophic fault such as a stuck top gate. figure 18. ltc2978 application circuit with crowbar protection on intermediate bus v pwr v in_en v in_sns v dacp0 v sensep0 v dacm0 v sensem0 v out_en0 refp refm ltc2978* v in <15v gnd v dd33 v dd33 v dd25 *some details omitted for clarity only one of eight channels shown v in c bypass 0.1f 0.01f 0.22f 0.01f 0.1f 220 mcr12dc 2907 0.1f 0.1f v out 2978 f18 run/ss sgnd v fb gnd dc/dc converter load 4.99k bat54 10k 100 68 v cc sense r sense 0.007 q1 si4894bdy ltc4210-3 timer gnd gate 24.3k 10k on
ltc2978 66 2978fc figure 19. channel fault management block diagram applications information channel 0 event processor page = 0 mfr_faultb00_response, page = 0 mfr_faultb01_response, page = 0 mfr_faultbz0_propagate_ch0 faultb00 mfr_faultbz1_propagate_ch0 channel 1 event processor page = 1 mfr_faultb00_response, page = 1 mfr_faultb01_response, page = 1 mfr_faultbz0_propagate_ch1 mfr_faultbz1_propagate_ch1 channel 2 event processor page = 2 mfr_faultb00_response, page = 2 mfr_faultb01_response, page = 2 mfr_faultbz0_propagate_ch2 mfr_faultbz1_propagate_ch2 channel 3 event processor page = 3 zone 0 zone 1 zone 0 zone 1 mfr_faultb00_response, page = 3 mfr_faultb01_response, page = 3 mfr_faultbz0_propagate_ch3 mfr_faultbz1_propagate_ch3 faultb01 channel 4 event processor page = 4 mfr_faultb10_response, page = 4 mfr_faultb11_response, page = 4 mfr_faultbz0_propagate_ch4 faultb10 mfr_faultbz1_propagate_ch4 channel 5 event processor page = 5 mfr_faultb10_response, page = 5 mfr_faultb11_response, page = 5 mfr_faultbz0_propagate_ch5 mfr_faultbz1_propagate_ch5 channel 6 event processor page = 6 mfr_faultb10_response, page = 6 mfr_faultb11_response, page = 6 mfr_faultbz0_propagate_ch6 mfr_faultbz1_propagate_ch6 channel 7 event processor page = 7 mfr_faultb10_response, page = 7 mfr_faultb11_response, page = 7 mfr_faultbz0_propagate_ch7 mfr_faultbz1_propagate_ch7 faulted_off faulted_off faulted_off faulted_off faulted_off faulted_off faulted_off faulted_off faultb11 2978 f19
ltc2978 67 2978fc applications information figure 20. typical connections between multiple ltc2978s multichannel fault management multichannel fault management is handled using the bidirectional faultbz n pins. the z designates the fault zone which is either 0 or 1. there are two fault zones in the ltc2978. each zone contains 4-channels. figure 19 illustrates the connections between channels and the faultbz n pins. ? the mfr_faul tbz0_propagate command acts like a programmable switch that allows faulted-off condi - tions from a particular channel (page) to propagate to either faultbz n output in that channels zone. the mfr_faultbz n _response command controls similar switches on the inputs to each channel that allow any channel to shut down in response to any combination of the faultbz n pins within a zone. channels responding to a faultbz n pin pulling low will attempt a new start sequence when the faultbz n pin in question is released by the faulted channel. ? to establish dependencies across fault zones, tie the fault pins together, e.g., faultb01 to faultb10. any channel can depend on any other. to disable all chan - nels in response to any channel faulting off, short all the faultbz n pins together, and set mfr_faultbz n_ propagate = 0x01 and mfr_faultbz n_response = 0x0f for all channels. ? a faultbz n pin can also be asserted low by an external driver in order to initiate an immediate off-sequence after a 10s deglitch delay. interconnect between multiple ltc2978s figure 20 shows how to interconnect the pins in a typical multi-ltc2978 array. ? all v in_sns lines should be tied together in a star type connection at the point where v in is to be sensed. this will minimize timing errors for the case where the on_off_config is confgured to start the ltc2978 based on v in and ignore the control line and the operation command. in multi-part applications that are sensitive to timing differences, it is recommended that the vin_share_enable bit of the mfr_config_all register be set high in order to allow share_clk to synchronize on/off sequencing in response to the vin_on and vin_off thresholds. ? connecting all v in_en lines together will allow selected faults on any dc/dc converters output in the array to shut off a common input switch. vin_sns vin_en sda scl alertb control0 control1 wdi/resetb faultb00 faultb01 faultb10 faultb11 share_clk pwrgd gnd ltc2978 n-1 vin_sns vin_en sda scl alertb control0 control1 wdi/resetb faultb00 faultb01 faultb10 faultb11 share_clk pwrgd gnd 2978 f20 ltc2978 n to v in of dc/dcs to input switch to host controller to other ltc2978s?10k equiv pull-up recommended on each line except share_clk (use 5.49k)
ltc2978 68 2978fc applications information figure 21. aborted on sequence due to channel 1 short ? alertb is typically one line in an array of pmbus converters. the ltc2978 allows a rich combination of faults and warnings to be propagated to the alertb pin. ? wdi/resetb can be used to put the ltc2978 in the power-on reset state. pull wdi/resetb low for at least t resetb to enter this state. ? the faultbz n lines can be connected together to create fault dependencies. figure 20 shows a confguration where a fault on any faultbz n will pull all others low. this is useful for arrays where it is desired to abort a start-up sequence in the event any channel does not come up (see figure 21). ? pwrgd refects the status of the outputs that are mapped to it by the mfr_pwrgd_en command. figure 19 shows all the pwrgd pins connected together, but any combination may be used. note that the latency of the pwrgd pin response may be in the range of 30ms to 185ms depending on adc mux settings. see electrical characteristics table note 6. a fast deassertion of pwrgd may be implemented by wire anding the v in_en pin with the pwrgd pin. when the uv fault threshold is crossed, v in_en will pull low if programmed to do so. see figure 22. figure 22. pwrgd deassert v controln v out0 ton_delay0 v out1 v out2 v outn bussed vfaultbz n pins ton_max_fault1 2978 f21 ton_delay1 ton_delay2 ton_delay n ? ? ? ? ? ? ltc2978 v in_en v dd33 fast pwrgd deassert pwrgd 4.7k 2978 f22
ltc2978 69 2978fc figure 23. application circuit for dc/dc converters with external feedback resistors applications information application circuits trimming and margining dc/dc converters with external feedback resistors figure 23 shows a typical application circuit for trimming/ margining a power supply with an external feedback network. the v sensep0 and v sensem0 differential inputs sense the load voltage directly, and a correction voltage is developed between the v dacp0 and v dacm0 pins by the closed-loop servo algorithm. v dacm0 is kelvin connected to the point-of-load gnd in order to minimize the effects of load induced grounding errors. the v dacp0 output is connected to the dc/dc converters feedback node through resistor r30. for this confguration, set b[0] in mfr_config_ltc2978 = 0. four-step resistor selection procedure for dc/dc converters with external feedback resistors the following four-step procedure should be used to calculate the resistor values required for the application circuit shown in figure 23. 1. assume values for feedback resistor r20 and the nominal dc/dc converter output voltage v dc(nom) , and solve for r10. v dc(nom) is the output voltage of the dc/dc converter when the ltc2978s v dacp0 pin is in a high impedance state. r10 is a function of r20, v dc(nom) , the voltage at the feedback node (v fb ) when the loop is in regulation, and the feedback nodes input current (i fb ). r10 = r20 ? v fb v dc(nom) C i fb ? r20 C v fb (1) 2. solve for the value of r30 that yields the maximum required dc/dc converter output voltage v dc(max) . when v dacp0 is at 0v, the output of the dc/dc converter is at its maximum voltage. r30 r20 ? v fb v dc(max) C v dc(nom) (2) 3. solve for the minimum value of v dacp0 thats needed to yield the minimum required dc/dc converter output voltage v dc(min) . the dac has two full-scale settings, 1.38v and 2.65v. in order to select the appropriate full-scale setting, calculate the minimum required v dacp0(f/s) output voltage: v dacp0(f /s) > v dc(nom) C v dc(min) ( ) ? r30 r20 + v fb (3) v pwr v dd33 v dd33 v dd25 v in_sns v dacp0 v sensep0 v dacm0 v sensem0 v out_en0 ltc2978* 0.1f 0.1f v in 4.5v < v ibus < 15v gnd *some details omitted for clarity only one of eight channels shown v in v out r20 r30 r10 2978 f23 run/ss sgnd v fb gnd dc/dc converter load 0.1f
ltc2978 70 2978fc figure 24. application circuit for dc/dc converters with trim pin applications information 4. recalculate the minimum, nominal, and maximum dc/dc converter output voltages and the resulting margining resolution. v dc(nom) = v fb ? 1 + r20 r10 ? ? ? ? ? ? + i fb ? r20 (4) v dc(min) = v dc(nom) C r20 r30 ? v dacp0(f /s) C v fb ( ) (5) v dc(max) = v dc(nom) + r20 r30 ? v fb (6) v res = r20 r30 ? v dacp0(f /s) 1024 v/dac lsb (7) trimming and margining dc/dc converters with a trim pin figure 24 illustrates a typical application circuit for trim - ming/margining the output voltage of a dc/dc converter with a trim pin. the ltc2978s v dacp0 pin connects to the trim pin through resistor r30, and the v dacm0 pin is connected to the converters point-of-load ground. for this confguration, set the dac polarity bit mfr_confg_ dac_pol in mfr_config_ltc2978 to 1. dc/dc converters with a trim pin are typically margined high or low by connecting an external resistor between the trim pin and either the v sensep or v sensem pin. the relationships between these resistors and the % change in the output voltage of the dc/dc converter are typically expressed as: r trim_down = r trim ? 50 down % ? r trim (8) r trim_up = r trim ? v dc ? 100 + up % ( ) 2 ? v ref ? up % ? 50 up % ? ? ? ? ? ? ? 1 ? ? ? ? ? ? ? ? (9) where r trim is the resistance looking into the trim pin, v ref is the trim pins open-circuit output voltage and v dc is the dc/dc converters nominal output voltage. up % and down % denote the percentage change in the converters output voltage when margining up or down, respectively. two-step resistor and dac full-scale voltage selection procedure for dc/dc converters with a trim pin the following two-step procedure should be used to cal - culate the resistor value for r30 and the required full-scale dac voltage (refer to figure 24). 1. solve for r30: r30 r trim ? 50 ? down % down % ? ? ? ? ? ? (10) v pwr v dd33 v dd33 v dd25 v in_sns v dacp0 v sensep0 v dacm0 v sensem0 v out_en0 ltc2978* 0.1f 0.1f v in 4.5v < v ibus < 15v gnd *some details omitted for clarity only one of eight channels shown v in v out + trim 2978 f24 on/offb v sense ? v sense + gnd dc/dc converter load r30 0.1f
ltc2978 71 2978fc applications information 2. calculate the maximum required output voltage for v dacp0 : v dac p0 1 + up % down % ? ? ? ? ? ? ? v ref (11) note: not all dc/dcs converters follow these trim equa - tions especially newer bricks. consult ltc field application engineering. measuring current odd numbered adc channels may be used to measure supply current. set the adc to high resolution mode to confgure for current measuring and improve sensitivity. note that no ov or uv faults or warnings are reported in this mode, but telemetry is available from the read_vout command using the 11-bit signed mantissa plus 5-bit signed exponent l11 data format. set the mfr_con - fig_ltc2978 bit b[9] = 1 in order to enable high res mode. the v out_en pin will assert low in this mode and cannot be used to control a dc/dc converter. the v dacp output pin is also unavailable. measuring current with a sense resistor a circuit for measuring current with a sense resistor is shown in figure 25. the balanced flter rejects both com - mon mode and differential mode noise from the output of the dc/dc converter. the flter is placed directly across the sense resistor in series with the dc/dc converters induc - tor. note that the current sense inputs must be limited to less than 6v with respect to ground. select r cm and c cm such that the flters corner frequency is < 1/10 the dc/dc converters switching frequency. this will result in a current sense waveform that offers a good compromise between the voltage ripple and the delay through the flter. a value 1k for r cm is suggested in order to minimize gain er - rors due to the current sense inputs internal resistance. measuring current with inductor dcr figure 26 shows the circuit for applications that require dcr current sense. a second order rc flter is required in these applications in order to minimize the ripple volt - age seen at the current sense inputs. a value of 1k is suggested for r cm1 and r cm2 in order to minimize gain errors due the current sense inputs internal resis - tance. c cm1 should be selected to provide cancellation of the zero created by the dcr and inductance, i.e. c cm1 = l/(dcr?? r cm1 ). c cm2 should be selected to provide a second stage corner frequency at < 1/10 of the dc/dc converters switching frequency. in addition, c cm2 needs to be much smaller than c cm1 in order to prevent signifcant loading of the flters frst stage. figure 25. sense resistor current sensing circuits figure 26. sense resistor current sensing circuits r cm r cm r sns 2978 f25 l load current c cm c cm ltc2978 v sensep1 v sensem1 r cm2 r cm2 r cm1 r cm1 dcr 2978 f26 l swx0 c cm2 c cm1 c cm1 c cm2 ltc2978 v sensep1 v sensem1
ltc2978 72 2978fc applications information single phase design example as a design example for a dcr current sense application, assume l = 2.2h, dcr = 10m, and f sw = 500khz. let r cm1 = 1k and solve for c cm1 : c cm1 2.2h 10m ? ? 1k ? = 220nf let r cm2 = 1k. in order to get a second pole at f sw /10 = 50khz: c cm2 ? 1 2 ? 50khz ? 1k = 3.18nf let c cm2 = 3.3nf. note that since c cm2 is much less than c cm1 the loading effects of the second stage flter on the matched frst stage are not signifcant. consequently, the delay time constant through the flter for the current sense waveform will be approximately 3s. measuring multiphase currents for current sense applications with more than one phase, rc averaging may be employed. figure 27 shows an example of this approach for a 3-phase system with dcr current sensing. the current sense waveforms are aver - aged together prior to being applied to the second stage of the flter consisting of r cm2 and c cm2 . because the r cm1 resistors for the three phases are in parallel, the value of r cm1 must be multiplied by the number of phases. also note that since the dcrs are effectively in parallel, the value for iout_cal_gain will be equal to the inductors dcr divided by the number of phases. care should to be taken in the layout of the multiphase inductors to keep the pcb trace resistance from the dc side of each inductor to the summing node balanced in order to provide the most accurate results. multiphase design example using the same values for inductance and dcr from the previous design example, the value for r cm1 will be 3k for a three phase dc/dc converter if c cm1 is left at 220nf. similarly, the value for iout_cal_gain will be dcr/3?=?3.33m. figure 27. multiphase dcr current sensing circuits r cm2 r c m1 r c m1 r c m1 r cm2 r cm1 /3 dcr dcr dcr l l l 2978 f27 to load swx3 swx2 swx1 ltc2978 i sensep i sensem c cm2 c cm1 c cm1 c cm2
ltc2978 73 2978fc figure 28. antialiasing filter on v sense lines figure 29. sensing negative voltages anti-aliasing filter considerations noisy environments require an anti-aliasing flter on the input to the ltc2978s adc. the r-c circuit shown in figure 28 is adequate for most situations. keep r40 = r50 200 to minimize adc gain errors, and select a value for capacitors c10 and c20 that doesnt add too much additional response time to the ov/uv supervisor, e.g. ? 10s (r = 100, c = 0.10f). sensing negative voltages figure 29 shows the ltc2978 sensing a negative power supply (v ee ). the r1/r2 resistor divider translates the negative supply voltage to the ltc2978s vsensem1 input while the vsensep1 input is tied to the refp pin which has a typical output voltage of 1.23v. the voltage divider should be confgured in order to present about 0.5v to the voltage sense inputs when the negative supply reaches its power_good_on threshold so that the current fowing out of the vsensemn pin is minimized to ~1a. the relationship between the power_good_on register value and the corresponding negative supply value can be expressed as: v ee = v refp v sensep sensem v ? (read_vout) where read_vout returns ? r2 r1 + 1 ? ? ? ? ? ? ? ? 1a ? r2 applications information v pwr v dd33 v dd33 v dd25 v in_sns v dacp0 v sensep0 v sensem0 v dacm0 v out_en0 ltc2978* 0.1f 0.1f v in 4.5v < v ibus < 15v gnd *some details omitted for clarity only one of eight channels shown v in v out r20 r30 r10 2978 f28 run/ss sgnd v fb gnd dc/dc converter load c10 c20 r50 r40 0.1f ltc2978 4.5v < v ibus < 15v gnd only one of eight channels shown, some details omitted for clarity power_good_on = 0.5v for v ee power_good = ?11.414v where v ee power_good = 0.1f 1.23v typ 2978 f29 v pwr sda scl alertb control faultb wdi/resetb share_clk asel0 asel1 wp v in_sns refm v sensep1 wdi/resetb v sensem1 refp pwrgd 0.1f r1 = 4.99k 1a at 0.5v r2 = 120k v ee = ?12v pmbus interface
ltc2978 74 2978fc applications information figure 30. ltc controller connections when v pwr is used connecting the usb to i 2 c/smbus/pmbus controller to the ltc2978 in system the ltc usb to i 2 c/smbus/pmbus controller can be interfaced to ltc2978s on the user's board for program - ming, telemetry and system debug. the controller, when used in conjunction with ltpowerplay software, provides a powerful way to debug an entire power system. failures are quickly diagnosed using telemetry, fault status registers and the fault log. the fnal confguration can be quickly developed and stored to the ltc2978's eeprom. figures 30 and 31 illustrate application schematics for powering, programming and communicating with one or more ltc2978's via the ltc i 2 c/smbus/pmbus controller regardless of whether or not system power is present. figure 30 shows the recommended schematic to use when the ltc2978 is powered by the system intermediate bus through its v pwr pin. v pwr v dd33 v dd33 v dd25 scl sda share_clk ltc2978 pin connections omitted for clarity 0.1f 4.5v to 15v 0.1f 0.1f wp gnd 2978 f30 5.49k 10k 49.9k si1303 to ltc usb to i 2 c/smbus/pmbus controller to/from other ltc2978s 150k repeat outlined circuit for every ltc2978 10k isolated 3.3v scl sda gnd
ltc2978 75 2978fc figure 31 shows the recommended schematic to use when the ltc2978 is powered by the system 3.3v through its v dd33 and v pwr pins. the ltc4212 ideal or'ing circuit allows either the controller or system to power the ltc2978. because of the controller's limited current sourcing capa - bility, only the ltc2978s, their associated pull up resistors and the i 2 c/smbus pull-up resistors should be powered from the ored 3.3v supply. in addition, any device sharing i 2 c/smbus bus connections with the ltc2978 should not have body diodes between the sda/scl pins and its v dd applications information node because this will interfere with bus communication in the absence of system power. the ltc controller's i 2 c/smbus connections are opto- isolated from the pc's usb. the 3.3v from the controller and the ltc2978's v dd33 pin can be paralleled because the ltc ldos that generate these voltages can be back - driven and draw <10a. the controller's 3.3v current limit is 100ma. figure 31. ltc controller connections when ltc2978 powered directly from 3.3v v pwr v dd33 v dd33 v dd25 scl sda share_clk ltc2978_3.3v ideal diode 0r?d 3.3v 0.1f 0.1f wp gnd 2978 f31 5.49k ltc2978 pin connections omitted for clarity to ltc usb to i 2 c/smbus/pmbus controller note: ltc controller i 2 c connections are opto-isolated isolated 3.3v from controller can be back driven and will only draw < 10a isolated 3.3v current limit = 100ma to/from other ltc2978s 10k 10k system 3.3v tp0101k-ssot23 v in gnd ctl sense gate stat ltc4412 isolated 3.3v scl sda gnd
ltc2978 76 2978fc applications information ltpowerplay : an interactive gui for digital power ltpowerplay is a powerful windows based development environment that supports linear technology digital power ics with eeprom, including the ltc2978 octal digital power supply manager. the software supports a variety of different tasks. you can use ltpowerplay to evaluate linear technology ics by connecting to a demo board system. ltpowerplay can also be used in an offine mode (with no hardware present) in order to build a multi-chip confguration fle that can be saved and reloaded at a later time. ltpowerplay provides unprecedented diagnostic and debug features. it becomes a valuable diagnostic tool during board bring-up to program or tweak the power management scheme in a system or to diagnose power issues when bringing up rails. ltpowerplay utilizes linear technology's usb-to-i 2 c/smbus/pmbus controller to communicate with one of many potential targets, includ- ing the dc1540 demo board set, the dc1508 socketed programming board, or a customer target system. the software also provides an automatic update feature to keep the software current with the latest set of device drivers and documentation. a great deal of context sensitive help is available within ltpowerplay along with several tutorial demos. complete information is available at: www.linear.com/ltpowerplay
ltc2978 77 2978fc figure 32. suggested screen pattern for die attach pad figure 33. connecting unused inputs to gnd applications information pcb assembly and layout suggestions bypass capacitor placement the ltc2978 requires 0.1f bypass capacitors between the v dd33 pins and gnd, the v dd25 pin and gnd, and the refp pin and refm pin. if the chip is being powered from the v pwr input, then that pin should also be bypassed to gnd by a 0.1f capacitor. in order to be effective, these capacitors should be made of high quality ceramic dielectric such as x5r or x7r and be placed as close to the chip as possible. exposed pad stencil design the ltc2978s package is thermally and electrically effcient. this is enabled by the exposed die attach pad on the under side of the package which must be soldered down to the pcb or mother board substrate. it is a good practice to minimize the presence of voids within the exposed pad inter-connection. total elimination of voids is diffcult, but the design of the exposed pad stencil is key. figure 32 shows a suggested screen print pattern. the proposed stencil design enables out-gassing of the solder paste during refow as well as regulating the fnished solder thickness. pc board layout mechanical stress on a pc board and soldering-induced stress can cause the ltc2978s reference voltage and voltage drift to shift. a simple way to reduce these stress- related shifts is to mount the ic near the short edge of the pc board, or in a corner. the board edge acts as a stress boundary, or a region where the fexure of the board is minimal. unused adc sense inputs connect all unused adc sense inputs (v sensep n or v sensemn ) to gnd. in a system where the inputs are connected to removable cards and may be left foating in certain situations, connect the inputs to gnd using 100k resistors. place the 100k resistors before any flter components, as shown in figure 33, to prevent loading of the flter. 2978 f32 100k 100k v sensep v sensep ltc2978 2978 f33
ltc2978 78 2978fc up package 64-lead plastic qfn (9mm 9mm) (reference ltc dwg # 05-08-1705 rev c) 9 .00 0.10 (4 sides) note: 1. drawing conforms to jedec package outline mo-220 variation wnjr-5 2. all dimensions are in millimeters 3. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 4. exposed pad shall be solder plated 5. shaded area is only a reference for pin 1 location on the top and bottom of package 6. drawing not to scale pin 1 top mark (see note 5) 0.40 0.10 6463 1 2 bottom view?exposed pad 7.15 0.10 7.15 0.10 7.50 ref (4-sides) 0.75 0.05 r = 0.10 typ r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (up64) qfn 0406 rev c recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 7.50 ref (4 sides) 7.15 0.05 7.15 0.05 8.10 0.05 9.50 0.05 0.25 0.05 0.50 bsc package outline pin 1 chamfer c = 0.35 package description please refer to http://www.linear.com/designtools/packaging/ for the most recent package drawings.
ltc2978 79 2978fc information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 10/11 all sections revised 1 - 80 c 3/12 change mfr_config name to mfr_config_ltc2978 changed text data log to fault log under eeprom related commands data_log comments elaborated on on_off_config command description added unused adc sense inputs section renumbered figure 33 to figure 34 19, 23,42 23 31 77 80 (revision history begins at rev b)
ltc2978 80 2978fc linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com ? linear technology corporation 2009 lt 0412 rev c ? printed in usa related parts typical application part number description comments ltc2970 dual i 2 c power supply monitor and margining controller ltc2974 quad digital power supply manager with eeprom accurate current measurement and supervision LTC3880 dual output polyphase ? step-down dc/dc controller with digital power system management figure 34. ltc2978 application circuit with 3.3v chip power v in v out r27 61 11 60 2 3 38 4 39 36 37 r37 r30 r17 r20 r10 run/ss sgnd v fb gnd dc/dc converter load load v dacp7 v sensep7 v sensem7 v dacm7 v out_en7 v dacp0 v sensep0 v sensem0 v dacm0 v out_en0 v in v out r26 58 10 59 64 1 r36 r16 run/ss sgnd v fb gnd dc/dc converter load v dacp6 v sensep6 v sensem6 ltc2978 v dacm6 v out_en6 v in v out r25 57 9 56 62 63 r35 r15 run/ss sgnd v fb gnd dc/dc converter load v dacp5 v sensep5 v sensem5 v dacm5 v out_en5 v in v out r24 54 8 55 52 53 r34 r14 run/ss sgnd v fb gnd 2978 f34 dc/dc converter load v dacp4 v sensep4 v sensem4 v dacm4 v out_en4 v in run/ss v out sgnd v fb gnd dc/dc converter 41 5 40 42 43 v dacp1 v sensep1 v sensem1 v dacm1 v out_en1 45 6 44 46 47 r32 r22 r12 load v dacp2 v sensep2 v sensem2 v dacm2 v out_en2 v in run/ss v out sgnd v fb gnd dc/dc converter in out en intermediate bus converter 51 7 12 10k 50 48 49 v dacp3 v sensep3 v sensem3 v dacm3 v out_en3 v in_en 10k 10k 10k 10k 5.49k 10k to/from other ltc2974s, ltc2978s and microcontroller 3.3v 3.3v 10k 10k 10k 10k 10k 23 faultb00 13 0.1f 3435 65 19 18 17 16 15 33 32 14 3.3v 24 faultb01 25 faultb10 26 faultb11 21 share_clk 27 sda 28 scl 29 alertb 30 control0 31 control1 20 pwrgd 22 wdi/resetb dnc refm refp gnd wp v dd25 v dd33 v dd33 v pwr asel1 asel0 v in_sns 0.1f 0.1f

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